2004 Mar 16
99
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
10.6
Host port for 16-bit extension of video data I/O (H port)
The H port, pins HPD, can be used to extend the data I/O paths to 16-bit.
The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled and are
dependent on the I port enable control. When I8_16 = 0, the HPD output is disabled.
Table 63
Signals dedicated to the host port
SYMBOL
PIN
I/O
DESCRIPTION
BIT
HPD7 to
HPD0
A13, D12, C12, B12,
A12, C11, B11 and A11
I/O 16-bit extension for digital I/O
(chrominance component)
IPE[1:0] 87H[1:0], ITRI[8FH[6]] and
I8_16[93H[6]]
10.7
Basic input and output timing diagrams for the
I and X ports
10.7.1
I
PORT OUTPUT TIMING
The following diagrams (Figs 39 to 45) illustrate the output
timing via the I port. IGPH and IGPV are indicated as
logic 1 active gate signals. If reference pulses are
programmed, these pulses are generated on the rising
edgeofthelogic 1activegates.Validdataisaccompanied
by the output data qualifier on pin IDQ. In addition, invalid
cycles are marked with output code 00H.
The IDQ output pin may be defined to be a gated clock
output signal (ICLK AND internal IDQ).
10.7.2
X
PORT INPUT TIMING
The input timing requirements at the X port are the same
as those for the I port output. However, the following
differences should be noted:
It is not necessary to mark invalid cycles with a 00H
code
No constraints on the input qualifier (can be a random
pattern)
XCLK may by a gated clock (XCLK AND external XDQ).
Remark
: All timings illustrated are given for an
uninterrupted output stream (no handshake with the
external hardware).
IPD[7:0]
IGPH
IDQ
ICLK
00
FF
00
00
SAV
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
MHB550
Fig.39 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 1).