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參數(shù)資料
| 型號： | SAA7108 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | PC-CODEC |
| 中文描述： | PC的編解碼器 |
| 文件頁數(shù)： | 79/202頁 |
| 文件大?。?/td> | 983K |
| 代理商： | SAA7108 |
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2004 Mar 16
79
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
9.3.2.2
Horizontal fine scaling (variable phase delay
filter; subaddresses A8H to AFH and
D8H to DFH)
Thehorizontalfinescaling(VPD)shouldoperateatscaling
ratios between
1
2
and 2 (0.8 and 1.6), but can also be
used for direct scaling in the range from
1
7.999
to
(theoretical) zoom 3.5 (restriction due to the internal data
path architecture), without prescaler.
In combination with the prescaler a compromise between
sharpness impression and alias can be found, which is
signal source and application dependent.
For the luminance channel a filter structure with 10 taps is
implemented, for the chrominance a filter with 4 taps.
Luminance and chrominance scale increments
(XSCY[12:0]A9H[4:0]A8H[7:0]andXSCC[12:0]ADH[4:0]
ACH[7:0]) are defined independently, but must be set in a
2 : 1 relationship in the actual data path implementation.
The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0]
AEH[7:0] can be used to shift the sample phases slightly.
XPHY[7:0] and XPHC[7:0] covers the phase offset range
7.999T to
1
32
T. The phase offsets should also be
programmed in a 2 : 1 ratio.
The underlying phase controlling DTO has a 13-bit
resolution.
According to the equations
and
The VPD covers the scale range from 0.125 to zoom 3.5.
The VPD acts equivalent to a polyphase filter with 64
possible phases. In combination with the prescaler, it is
possible to get high accurate samples from a highly
anti-aliased integer downscaled input picture.
9.3.3
V
ERTICAL SCALING
The vertical scaler of the SAA7108E; SAA7109E decoder
part consists of a line FIFO buffer for line repetition and the
vertical scaler block, which implements the vertical scaling
on the input data stream in 2 different operational modes
from theoretical zoom by 64 down to icon size
1
64
. The
vertical scaler is located between the BCS and horizontal
fine scaler, so that the BCS can be used to compensate for
the DC gain amplification of the ACM mode (see
Section 9.3.3.2) as the internal RAMs are only 8-bit wide.
9.3.3.1
Line FIFO buffer (subaddresses 91H, B4H and
C1H, E4H)
The line FIFO buffer is a dual ported RAM structure for
768 pixels, with asynchronous write and read access. The
line buffer can be used for various functions, but not all
functions may be available simultaneously.
Thelinebuffercanbufferacompleteunscaledactivevideo
line or more than one shorter lines (only for non-mirror
mode), for selective repetition for vertical zoom-up.
For zooming up from 240 lines to 288 lines e.g., every
fourth line is requested (read) twice from the vertical
scaling circuitry for calculation.
For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling
scheme (MPEG, video phone, Indeo YUV-9) to ITU like
sampling scheme 4 : 2 : 2, the chrominance line buffer is
read twice or four times, before being refilled again by the
source. By means of the input acquisition window
definition it has to be preserved, that the processing starts
with a line containing luminance and chrominance
information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits
FSC[2:1] 91H[2:1] define the distance between the Y/C
lines. In case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1
have to be set to ‘00’.
The line buffer can also be used for mirroring, i.e. for
flipping the image left to right, for the vanity picture in video
phone application (bit YMIR[B4H[4]]). In mirror mode only
one active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as excessive pipeline buffer
for discontinuous and variable rate transfer conditions at
the expansion port or image port.
9.3.3.2
Vertical scaler (subaddresses B0H to BFH and
E0H to EFH)
Vertical scaling of any ratio from 64 (theoretical zoom)
to
1
63
(icon) can be applied.
The vertical scaling block consists of another line delay,
and the vertical filter structure, that can operate in two
different modes. These are the Linear Phase Interpolation
(LPI) and Accumulation (ACM) modes, controlled by
YMODE[B4H[0]].
XSCY[12:0]
1024
XPSC[5:0]
×
Npix_out
×
=
XSCC[12:0]
XSCY[12:0]
--------------2
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7108E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
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