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參數(shù)資料
| 型號(hào)： | SAA7108 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | Codec |
| 英文描述： | PC-CODEC |
| 中文描述： | PC的編解碼器 |
| 文件頁(yè)數(shù)： | 23/202頁(yè) |
| 文件大?。?/td> | 983K |
| 代理商： | SAA7108 |
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2004 Mar 16
23
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Alternatively, the device can be triggered by auxiliary
codes in a ITU-R BT.656 data stream via PD7 to PD0.
Only vertical frequencies of 50 and 60 Hz are allowed with
the SAA7108E; SAA7109E. In slave mode, it is not
possible to lock the encoders colour carrier to the line
frequency with the PHRES bits.
In the (more common) master mode, the time base of the
circuit is continuously free-running. The IC can output a
frame sync at pin FSVGC, a vertical sync at pin VSVGC, a
horizontal sync at pin HSVGC and a composite blanking
signal at pin CBO. All of these signals are defined in the
PIXCLK domain. The duration of HSVGC and VSVGC are
fixed,theyare64 clocksforHSVGCand1 lineforVSVGC.
The leading slopes are in phase and the polarities can be
programmed.
The input line length can be programmed. The field length
is always derived from the field length of the encoder and
the pixel clock frequency that is being used.
CBO acts as a data request signal. The circuit accepts
input data at a programmable number of clocks after CBO
goes active. This signal is programmable and it is possible
to adjust the following (see Figs 48 and 49):
The horizontal offset
The length of the active part of the line
The distance from active start to first expected data
The vertical offset separately for odd and even fields
The number of lines per input field.
In most cases, the vertical offsets for odd and even fields
are equal. If they are not, then the even field will start later.
The SAA7108E; SAA7109E will also request the first input
lines in the even field, the total number of requested lines
will increase by the difference of the offsets.
As stated above, the circuit can be programmed to accept
the look-up and cursor data in the first 2 lines of each field.
The timing generator provides normal data request pulses
fortheselines;thedurationisthesameasforregularlines.
The additional request pulses will be suppressed with
LUTL set to logic 0; see Table 139. The other vertical
timings do not change in this case, so the first active line
can be number 2, counted from 0.
8.16
I
2
C-bus interface
The I
2
C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
read, except two read only status bytes.
The register bit map consists of an RGB Look-Up Table
(LUT), a cursor bit map and control registers. The LUT
contains three banks of 256 bytes, where each RGB triplet
is assigned to one address. Thus a write access needs the
LUT address and three data bytes following subaddress
FFH. For further write access auto-incrementing of the
LUT address is performed. The cursor bit map access is
similar to the LUT access but contains only a single byte
per address.
The I
2
C-bus slave address is defined as 88H.
8.17
Programming the graphics acquisition scaler
of the video encoder
In order to program the graphics acquisition scaler it is first
necessary to determine the input and output field timings.
The timings are controlled by decoding binary counters
that index the position in the current line and field
respectively. In both cases, 0 means the start of the sync
pulse.
At 60 Hz, the first visible pixel has the index 256,
710 pixels can be encoded; at 50 Hz, the index is 284,
702 pixels can be visible. Some variables are defined
below:
InPix: the number of active pixels per input line
InPpl: the length of the entire input line in pixel clocks
InLin: the number of active lines per input field/frame
TPclk: the pixel clock period
OutPix: the number of active pixels per output line
OutLin: the number of active lines per output field
TXclk: the encoder clock period (37.037 ns).
The output lines should be centred on the screen. It should
be noted that the encoder has 2 clocks per pixel;
see Table 106.
ADWHS = 256 + 710
OutPix (60 Hz);
ADWHS = 284 + 702
OutPix (50 Hz);
ADWHE = ADWHS + OutPix
×
2 (all frequencies)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7108AE | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:HD-CODEC |
| SAA7108E | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109A | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:HD-CODEC |
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