2004 Mar 16
168
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.2.2.27 Subaddress 1FH
Table 176
Status byte video decoder; 1FH[7:0]; read only register
18.2.3
P
ROGRAMMING REGISTER AUDIO CLOCK GENERATION
See equations in Section 9.6 and examples in Tables 51 and 52.
18.2.3.1
Subaddresses 30H to 32H
Table 177
Audio master clock (AMCLK) cycles per field
BIT
DESCRIPTION
I
2
C-BUS
CONTROL
BIT
OLDSB
14H[2]
VALUE
FUNCTION
7
status bit for interlace detection
INTL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
non-interlaced
interlaced
both loops locked
unlocked
locked
unlocked
50 Hz
60 Hz
not active
active
not active
active
not active
active
not active
active
not active
active
not active
active
not active
active
6
status bit for horizontal and vertical loop
HLVLN
0
status bit for locked horizontal frequency
HLCK
1
5
identification bit for detected field frequency
FIDT
4
gain value for active luminance channel is
limited; maximum (top)
GLIMT
3
gain value for active luminance channel is
limited; minimum (bottom)
GLIMB
2
white peak loop is activated
WIPA
1
copy protected source detected according to
macrovision version up to 7.01
COPRO
0
slow time constant active in WIPA mode
SLTCA
1
0
ready for capture (all internal loops locked)
RDCAP
0
colour signal in accordance with selected
standard has been detected
CODE
1
SUBADDRESS
CONTROL BITS 7 TO 0
30H
31H
32H
ACPF7
ACPF15
ACPF6
ACPF14
ACPF5
ACPF13
ACPF4
ACPF12
ACPF3
ACPF11
ACPF2
ACPF10
ACPF1
ACPF9
ACPF17
ACPF0
ACPF8
ACPF16