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參數(shù)資料
| 型號(hào)： | SAA7108 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | PC-CODEC |
| 中文描述： | PC的編解碼器 |
| 文件頁(yè)數(shù)： | 80/202頁(yè) |
| 文件大?。?/td> | 983K |
| 代理商： | SAA7108 |
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2004 Mar 16
80
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
LPI mode
: In the linear phase interpolation mode
(YMODE = 0)twoneighbouringlinesofthesourcevideo
stream are added together, but weighted by factors
corresponding to the vertical position (phase) of the
target output line relative to the source lines. This linear
interpolation has a 6-bit phase resolution, which equals
64 intra line phases. It interpolates between two
consecutive input lines only. The LPI mode should be
applied for scaling ratios around 1 (down to
1
2
),
it must
be applied for vertical zooming
.
ACM mode
: The vertical Accumulation (ACM) mode
(YMODE = 1) represents a vertical averaging window
over multiple lines, sliding over the field. This mode also
generates phase correct output lines. The averaging
window length corresponds to the scaling ratio, resulting
in an adaptive vertical low-pass effect, to greatly reduce
aliasing artefacts. ACM can be applied for downscales
only from ratio 1 down to
1
64
. ACM results in a scale
dependent
DC gain amplification
, which has to be
precorrected by the BCS control of the scaler part.
The phase and scale controlling DTO calculates in 16-bit
resolution, controlled by parameters YSCY[15:0] B1H[7:0]
B0H[7:0]andYSCC[15:0]B3H[7:0]B2H[7:0],continuously
over the entire filed. A start offset can be applied to the
phase processing by means of the parameters
YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and
YPC3[7:0] to YPC0[7:0]inBBH[7:0] to B8H[7:0].Thestart
phase covers the range of
255
32
to
1
32
lines offset.
By programming appropriate, opposite, vertical start
phase values (subaddresses B8H to BFH and
E8H to EFH) depending on odd/even field ID of the source
videostreamandA/Bpagecycle,frameIDconversionand
field rate conversion are supported (i.e. de-interlacing,
re-interlacing).
Figs 36 and 37 and Tables 42 and 43 describe the use of
the offsets.
Remark: The vertical start phase, as well as the
scaling ratio are defined independently for luminance
and chrominance channels, but must be set to the
same values in the actual implementation for accurate
4 : 2 : 2 output processing.
The vertical processing communicates on its input side
with the line FIFO buffer. The scale related equations are:
Scaling increment calculation for ACM and LPI mode,
downscale and zoom: YSCY[15:0] and YSCC[15:0]
BCS value to compensate DC gain in ACM mode
(contrast and saturation have to be set): CONT[7:0]
A5H[7:0] respectively SATN[7:0] A6H[7:0]
Nline_in
, or
9.3.3.3
Use of the vertical phase offsets
As shown in Section 9.3.1.3, the scaler processing may
run randomly over the interlaced input sequence.
Additionally the interpretation and timing between ITU 656
field ID and real-time detection by means of the state of
H sync at the falling edge of V sync may result in different
field ID interpretation.
A vertically scaled interlaced output also gets a larger
vertical sampling phase error, if the interlaced input fields
are processed, without regard to the actual scale at the
starting point of operation (see Fig.36).
The four events to be considered are illustrated in Fig.37.
In Tables 42 and 43
PHO
is a usable common phase
offset.
It should be noted that the equations in Fig.37 also
produce an interpolated output for the unscaled case, as
the geometrical reference position for all conversions is
the position of the first line of the lower field (see Table 42).
If there is no need for UP-LO and LO-UP conversion and
the input field ID is the reference for the back-end
operation, then it is UP-LO = UP-UP and LO-UP = LO-LO
and the
1
2
line phase shift (PHO + 16) that can be
skipped; this case is given in Table 43.
The SAA7108E; SAA7109E supports 4 phase offset
registers per task and component (luminance and
chrominance). The value of 20H represents a phase shift
of one line.
The registers are assigned to the following events;
e.g. subaddresses B8H to BBH:
B8H: 00 = input field ID 0, task status bit 0 (toggle
status, see Section 9.3.1.3)
B9H: 01 = input field ID 0, task status bit 1
BAH: 10 = input field ID 1, task status bit 0
BBH: 11 = input field ID 1, task status bit 1.
lower integer of
=
1024
Nline_out
×
lower integer of
Nline_out
64
×
=
lower integer of
YSCY[15:0]
64
×
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7108E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
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