2004 Mar 16
91
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
9.6.2
S
IGNALS
ASCLK
AND
ALRCLK
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for
channel-select. The frequencies of these signals are defined by the parameters:
SDIV[5:0] 38H[5:0] according to the equation:
LRDIV[5:0] 39H[5:0] according to the equation:
See Table 52 for examples.
Table 52
Programming examples for ASCLK/ALRCLK clock generation
9.6.3
O
THER CONTROL SIGNALS
Further control signals are available to define reference clock edges and vertical references; see Table 53
Table 53
Control signals
AMXCLK
(MHz)
ASCLK
(kHz)
SDIV
ALRCLK
(kHz)
LRDIV
DECIMAL
HEX
DECIMAL
HEX
12.288
1536
768
1411.2
2822.4
1024
2048
3
7
3
1
3
1
03
07
03
01
03
01
48
16
8
16
32
16
32
10
08
10
10
10
10
11.2896
44.1
8.192
32
CONTROL
SIGNAL
DESCRIPTION
APLL[3AH[3]]
Audio PLL mode:
0: PLL closed
1: PLL open
Audio Master clock Vertical Reference:
0: internal vertical reference
1: external vertical reference
ALRCLK Phase:
0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1: do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
ASCLK Phase:
0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1: do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
AMVR[3AH[2]]
LRPH[3AH[1]]
SCPH[3AH[0]]
f
ASCLK
f
SDIV
1
+
(
)
2
×
-------------------------------------
=
SDIV[5:0]
f
2f
ASCLK
-------------------
1
–
=
f
ALRCLK
f
2
×
LRDIV
=
LRDIV[5:0]
f
ALRCLK
2f
=