
2004 Mar 16
187
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.2.5.10 Subaddresses A4H to A6H
Table 227
Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]]
Table 228
Luminance contrast control; register set A [A5H[7:0]] and B [D5H[7:0]]
Table 229
Chrominance saturation control; register set A [A6H[7:0]] and B [D6H[7:0]]
18.2.5.11 Subaddresses A8H to AEH
Table 230
Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]]
Note
1.
Bits XSCY[15:13] are reserved and are set to logic 0.
LUMINANCE
BRIGHTNESS CONTROL
CONTROL BITS 7 TO 0
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
Value = 0
Nominal value = 128
Value = 255
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
LUMINANCE CONTRAST
CONTROL
CONTROL BITS 7 TO 0
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
Gain = 0
Gain =
1
64
Nominal gain = 64
Gain =
127
64
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
CHROMINANCE
SATURATION CONTROL
CONTROL BITS 7 TO 0
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
Gain = 0
Gain =
1
64
Nominal gain = 64
Gain =
127
64
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
HORIZONTAL LUMINANCE
SCALING INCREMENT
CONTROL BITS
A [A9H[7:4]]
B [D9H[7:4]]
A [A9H[3:0]]
B [D9H[3:0]]
A [A8H[7:4]]
B [D8H[7:4]]
A [A8H[3:0]]
B [D8H[3:0]]
XSCY[15:12]
(1)
XSCY[11:8]
XSCY[7:4]
XSCY[3:0]
Scale =
1024
1
(theoretical) zoom
Scale =
1024
294
, lower limit defined by
data path structure
Scale =
1024
1023
zoom
Scale = 1, equals 1024
Scale =
1024
1025
downscale
Scale =
1024
8191
downscale
0000
0000
0000
0001
0000
0010
0000
0110
0000
0000
0000
0001
0011
0100
0100
1111
1111
0000
0000
1111
1111
0000
0001
1111