
2004 Mar 16
108
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
9-bit analog-to-digital converters
B
φ
diff
analog bandwidth
differential phase
(amplifier plus anti-alias
filter bypassed)
differential gain (amplifier
plus anti-alias filter
bypassed)
ADC clock frequency
DC differential linearity
error
DC integral linearity error
at
3 dB
7
2
MHz
deg
G
diff
2
%
f
clk(ADC)
DLE
dc(d)
12.8
0.7
14.3
MHz
LSB
ILE
dc(i)
Digital inputs
1
LSB
V
IL(SDAd,SCLd)
LOW-level input voltage
pins SDAd and SCLd
0.5
+0.3V
DDD
V
V
IH(SDAd,SCLd)
HIGH-level input voltage
pins SDAd and SCLd
V
IL(XTALId)
LOW-level CMOS input
voltage pin XTALId
V
IH(XTALId)
HIGH-level CMOS input
voltage pin XTALId
V
IL(n)
LOW-level input voltage all
other inputs
V
IH(n)
HIGH-level input voltage
all other inputs
I
LI
input leakage current
I
LI/O
I/O leakage current
C
i
input capacitance
Digital outputs;
note 1
0.7V
DDD
V
DDD
+ 0.5
V
0.3
+0.8
V
2.0
V
DDD
+ 0.3
V
0.3
+0.8
V
2.0
5.5
V
1
10
8
μ
A
μ
A
pF
I/O at high-impedance
V
OL(SDAd)
LOW-level output voltage
pin SDAd
LOW-level output voltage
for clocks
HIGH-level output voltage
for clocks
LOW-level output voltage
all other digital outputs
HIGH-level output voltage
all other digital outputs
SDAd at 3 mA sink current
0.4
V
V
OL(clk)
0.5
+0.6
V
V
OH(clk)
2.4
V
DDD
+ 0.5
V
V
OL
0
0.4
V
V
OH
2.4
V
DDD
+ 0.5
V
Clock output timing (LLC and LLC2);
note 2
C
L(LLC)
T
cy
output load capacitance
cycle time
15
35
70
50
39
78
pF
ns
ns
pin LLC
pin LLC2
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT