2004 Mar 16
189
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Table 235
Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]]
Table 236
Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]]; note 1
Note
1.
X = don’t care.
Table 237
Vertical chrominance phase offset ‘00’; register set A [B8H[7:0]] and B [E8H[7:0]]
Table 238
Vertical luminance phase offset ‘00’; register set A [BCH[7:0]] and B [ECH[7:0]]
VERTICAL CHROMINANCE
SCALING INCREMENT
CONTROL BITS
A [B3H[7:4]]
B [E3H[7:4]]
A [B3H[3:0]]
B [E3H[3:0]]
A [B2H[7:4]]
B [E2H[7:4]]
A [B2H[3:0]]
B [E2H[3:0]]
YSCC[15:12]
YSCC[11:8]
YSCC[7:4]
YSCC[3:0]
This value must be set to the
luminance value YSCY[15:0]
0000
1111
0000
1111
0000
1111
0001
1111
VERTICAL SCALING MODE CONTROL
CONTROL BITS 4 AND 0
YMIR
YMODE
Vertical scaling performs linear interpolation between lines
Vertical scaling performs higher order accumulating interpolation, better alias
suppression
No mirroring
Lines are mirrored
X
X
0
1
0
1
X
X
VERTICAL CHROMINANCE PHASE
OFFSET
CONTROL BITS 7 TO 0
YPC07
YPC06
YPC05
YPC04
YPC03
YPC02
YPC01
YPC00
Offset = 0
Offset =
32
32
= 1 line
Offset =
255
32
lines
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
VERTICAL LUMINANCE PHASE
OFFSET
CONTROL BITS 7 TO 0
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
Offset = 0
Offset =
32
32
= 1 line
Offset =
255
32
lines
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1