2004 Mar 16
133
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Table 104
Subaddress 6FH
Table 105
Logic levels and function of CCEN
Table 106
Subaddresses 70H to 72H
Table 107
Subaddress 73H
Table 108
Subaddress 74H
Table 109
Subaddress 75H
DATA
BYTE
LOGIC
LEVEL
0
1
DESCRIPTION
CCEN
TTXEN
enables individual line 21 encoding; see Table 105
disables teletext insertion; default after reset
enables teletext insertion
selects the actual line, where Closed Caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
SCCLN
DATA BYTE
DESCRIPTION
CCEN1
CCEN0
0
0
1
1
0
1
0
1
line 21 encoding off; default after reset
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
DATA BYTE
DESCRIPTION
ADWHS
active display window horizontal start; defines the start of the active TV display portion after
the border colour
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
active display window horizontal end; defines the end of the active TV display portion before
the border colour
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
ADWHE
DATA BYTE
DESCRIPTION
REMARKS
TTXHS
start of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0); see Fig.50
TTXHS = 42H; is default after
reset if strapped to PAL
TTXHS = 54H; is default after
reset if strapped to NTSC
DATA BYTE
DESCRIPTION
REMARKS
TTXHD
indicates the delay in clock cycles between rising edge
of TTXRQ output signal on pin TTXRQ_XCLKO2
(CLK2EN = 0) and valid data at pin TTX_SRES
minimum value: TTXHD = 2; is
default after reset
DATA BYTE
DESCRIPTION
CSYNCA
advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks