2004 Mar 16
192
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
19.2
Audio clock generation part
The given values force the following behaviour of the SAA7108E; SAA7109E audio clock generation part:
Used crystal is 24.576 MHz
Expected field frequency is 59.94 Hz (e.g. NTSC M standard)
Generated audio master clock frequency at pin AMCLK is 256
×
44.1 kHz = 11.2896 MHz
AMCLK is externally connected to AMXCLK (short-cut between pins K12 and J12)
ASCLK = 32
×
44.1 kHz = 1.4112 MHz
ALRCLK is 44.1 kHz.
Table 240
Audio clock part set-up values
Note
1.
All X values must be set to logic 0.
SUB
ADDRESS
(HEX)
REGISTER FUNCTION
BIT NAME
(1)
START VALUES
7
6
5
4
3
2
1
0
HEX
30
audio master clock cycles per
field; bits 7 to 0
audio master clock cycles per
field; bits 15 to 8
audio master clock cycles per
field; bits 17 and 16
reserved
audio master clock nominal
increment; bits 7 to 0
audio master clock nominal
increment; bits 15 to 8
audio master clock nominal
increment; bits 21 to 16
reserved
clock ratio AMXCLK to ASCLK
clock ratio ASCLK to ALRCLK
audio clock generator basic
set-up
reserved
ACPF7 to ACPF0
1
0
1
1
1
1
0
0
BC
31
ACPF15 to ACPF8
1
1
0
1
1
1
1
1
DF
32
X, X, X, X, X, X, ACPF17 and
ACPF16
X, X, X, X, X, X, X, X
ACNI7 to ACNI0
0
0
0
0
0
0
1
0
02
33
34
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
00
CD
35
ACNI15 to ACNI8
1
1
0
0
1
1
0
0
CC
36
X, X, ACNI21 to ACNI16
0
0
1
1
1
0
1
0
3A
37
38
39
3A
X, X, X, X, X, X, X, X
X, X, SDIV5 to SDIV0
X, X, LRDIV5 to LRDIV0
X, X, X, X, APLL, AMVR,
LRPH, SCPH
X, X, X, X, X, X, X, X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
00
03
10
00
3B to 3F
0
0
0
0
0
0
0
0
00