2004 Mar 16
151
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.2.2.3
Subaddress 02H
Table 151
Analog input control 1 (AICO1); 02H[7:0]
Note
1.
To take full advantage of the Y/C modes 6 to 9 the I
2
C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
BIT
DESCRIPTION
SYMBOL
VALUE
FUNCTION
7 and 6
analog function select;
see Fig.14
FUSE[1:0]
00
01
10
11
00
01
10
11
0000
amplifier plus anti-alias filter bypassed
amplifier active
amplifier plus anti-alias filter active
off
±
1 LSB
±
2 LSB
±
3 LSB
Mode 0
: CVBS (automatic gain) from AI11 (pin P13);
see Fig.57
Mode 1
: CVBS (automatic gain) from AI12 (pin P11);
see Fig.58
Mode 2
: CVBS (automatic gain) from AI21 (pin P10);
see Fig.59
Mode 3
: CVBS (automatic gain) from AI22 (pin P9);
see Fig.60
Mode 4
: CVBS (automatic gain) from AI23 (pin P7);
see Fig.61
Mode 5
: CVBS (automatic gain) from AI24 (pin P6);
see Fig.62
Mode 6
: Y (automatic gain) from AI11 (pin P13) + C (gain
adjustable via GAI28 to GAI20) from AI21 (pin P10);
note 1; see Fig.63
Mode 7
: Y (automatic gain) from AI12 (pin P11) + C (gain
adjustable via GAI28 to GAI20) from AI22 (pin P9); note 1;
see Fig.64
Mode 8
: Y (automatic gain) from AI11 (pin P13) + C (gain
adapted to Y gain) from AI21 (pin P10); note 1; see Fig.65
Mode 9
: Y (automatic gain) from AI12 (pin P11) + C (gain
adapted to Y gain) from AI22 (pin P9); note 1; see Fig.66
Modes 10 to 15
: reserved
5 and 4
update hysteresis for
9-bit gain; see Fig.15
GUDL[1:0]
3 to 0
mode selection
MODE[3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
to
1111