
2004 Mar 16
126
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Table 77
Subaddress 1BH
Table 78
Subaddresses 26H and 27H
Table 79
Subaddress 28H
Table 80
Subaddress 29H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
MSM
0
1
0
1
0
1
0
1
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset
monitor sense mode on
check comparator at DAC on pin C8 is active, output is loaded
check comparator at DAC on pin C8 is inactive, output is not loaded
check comparator at DAC on pin C7 is active, output is loaded
check comparator at DAC on pin C7 is inactive, output is not loaded
check comparator at DAC on pin C6 is active, output is loaded
check comparator at DAC on pin C6 is inactive, output is not loaded
RCOMP
(read only)
GCOMP
(read only)
BCOMP
(read only)
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
WSS
wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
wide screen signalling output is disabled; default after reset
wide screen signalling output is enabled
WSSON
0
1
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
BS
starting point of burst in clock cycles
PAL: BS = 33 (21H); default after reset if
strapping pin G1 tied HIGH
NTSC: BS = 25 (19H); default after reset if
strapping pin G1 tied LOW
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
SRES
0
1
pin C3 accepts a teletext bit stream (TTX)
pin C3 accepts a sync reset input (SRES)
default after reset
a HIGH impulse resets synchronization of the
encoder (first field, first line)
PAL: BE = 29 (1DH); default after reset if
strapping pin G1 tied HIGH
NTSC: BE = 29 (1DH); default after reset if
strapping pin G1 tied LOW
BE
ending point of burst in clock cycles