
2004 Mar 16
66
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
MHB540
VGATE
VSTO[8:0] = 134H
VSTA[8:0] = 15H
(a) 1st field
CVBS
ITU counting
single field counting
1
1
2
2
3
3
4
4
5
5
6
6
7
7
...
...
22
22
625
312
624
311
623
310
622
309
23
23
FID
HREF
F_ITU656
V123
(1)
VGATE
CVBS
ITU counting
single field counting
FID
HREF
F_ITU656
V123
(1)
VSTO[8:0] = 134H
VSTA[8:0] = 15H
(b) 2nd field
313
313
314
1
315
2
316
3
317
4
318
5
319
6
...
...
335
22
312
312
311
311
310
310
309
309
336
23
Fig.29 Vertical timing diagram for 50 Hz/625 line systems.
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during
the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
For further information see programming section, Tables 167, 168 and 169.
NAME
RTS0 (PIN K13)
RTS1 (PIN L10)
XRH (PIN N2)
XRV (PIN L5)
X
X
HREF
F_ITU656
V123
VGATE
FID
X
X
X
X
X
X
X
X
X