2004 Mar 16
132
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Table 99
Subaddress 6DH
Table 100
Subaddress 6EH
Table 101
Logic levels and function of PHRES
Table 102
Logic levels and function of LDEL
Table 103
Logic levels and function of FLC
DATA BYTE
DESCRIPTION
VTRIG
sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
BLCKON
0
1
encoder in normal operation mode; default after reset
output signal is forced to blanking level
selects the phase reset mode of the colour subcarrier generator; see Table 101
selects the delay on luminance path with reference to chrominance path;
see Table 102
field length control; see Table 103
PHRES
LDEL
FLC
DATA BYTE
DESCRIPTION
PHRES1
PHRES0
0
0
1
1
0
1
0
1
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
DATA BYTE
DESCRIPTION
LDEL1
LDEL0
0
0
1
1
0
1
0
1
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
DATA BYTE
DESCRIPTION
FLC1
FLC0
0
0
1
1
0
1
0
1
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz