2004 Mar 16
195
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Table 243
Scaler and interface configuration examples
I
2
C-BUS
ADDRESS
(HEX)
MAIN FUNCTION
EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4
HEX
DEC
HEX
DEC
HEX
DEC
HEX
DEC
Global settings
80
task enable, IDQ and back-end clock
definition
XCLK output phase and X port output enable
IGPH, IGPV, IGP0 and IGP1 output definition
signal polarity control and I port byte
swapping
FIFO flag thresholds and video/text
arbitration
ICLK and IDQ output phase and I port enable
power save control and software reset
10
10
10
10
83
84
85
01
A0
10
01
C5
09
00
A0
10
00
A0
10
86
45
40
45
45
87
88
01
F0
01
F0
01
F0
01
F0
Task A: scaler input configuration and output format settings
90
91
92
93
task handling
scaler input source and format definition
reference signal definition at scaler input
I port output formats and configuration
00
08
10
80
00
08
10
40
00
18
10
80
00
38
10
84
Input and output window definition
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
horizontal input offset (XO)
10
00
D0
02
0A
00
F2
00
D0
02
F0
00
16
720
10
242
720
240
10
00
C0
02
0A
00
22
01
00
03
20
01
16
704
10
290
768
288
10
00
D0
02
0A
00
F2
00
60
01
20
01
16
720
10
242
352
288
10
00
D0
02
0A
00
22
01
C8
00
50
00
16
720
10
290
200
80
horizontal input (source) window length (XS)
vertical input offset (YO)
vertical input (source) window length (YS)
horizontal output (destination) window length
(XD)
vertical output (destination) window length
(YD)
Prefiltering and prescaling
A0
A1
A2
A4
A5
A6
integer prescale (value ‘00’ not allowed)
accumulation length for prescaler
FIR prefilter and prescaler DC normalization
scaler brightness control
scaler contrast control
scaler saturation control
01
00
00
80
40
40
01
00
00
80
40
40
02
02
AA
80
40
40
02
03
F2
80
11
11
128
64
64
128
64
64
128
64
64
128
17
17