2004 Mar 16
178
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.2.5.3
Subaddress 88H
Table 205
Power save control; global set 88H[7:4]; note 1
Notes
1.
2.
X = don’t care.
Bit SWRST is now located here.
Table 206
Power save control; global set 88H[3] and 88H[1:0]; note 1
Note
1.
X = don’t care.
POWER SAVE CONTROL
CONTROL BITS 7 TO 4
CH4EN
CH2EN
SWRST
(2)
DPROG
DPROG = 0 after reset
DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit
shows a logic 0 a power-up or start-up fail has occurred
Scaler path is reset to its idle state, software reset
Scaler is switched back to operation
AD1x analog channel is in power-down mode
AD1x analog channel is active
AD2x analog channel is in power-down mode
AD2x analog channel is active
X
X
X
X
X
X
0
1
X
X
X
X
0
1
X
X
0
1
X
X
0
1
X
X
X
X
X
X
X
X
X
X
POWER SAVE CONTROL
CONTROL BITS 3, 1 AND 0
SLM3
SLM1
SLM0
Decoder and VBI slicer are in operational mode
Decoder and VBI slicer are in Power-down mode; scaler only operates, if scaler
input and ICLK source is the X port (refer to subaddresses 80H and 91H/C1H)
Scaler is in operational mode
Scaler is in Power-down mode; scaler in Power-down stops I port output
Audio clock generation active
Audio clock generation in Power-down and output disabled
X
X
X
X
0
1
X
X
0
1
0
1
X
X
X
X
X
X