
2004 Mar 16
173
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Table 193
Global control 1; global set 80H[3:0]; note 1
Notes
1.
2.
Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
X = don’t care.
18.2.5.2
Subaddresses 83H to 87H
Table 194
X port I/O enable and output clock phase control; global set 83H[5:4]
Table 195
X port I/O enable and output clock phase control; global set 83H[2:0]
Note
1.
X = don’t care
I PORT AND SCALER BACK-END CLOCK SELECTION
CONTROL BITS 3 TO 0
ICKS3
ICKS2
ICKS1
ICKS0
ICLK output and back-end clock is line-locked clock LLC from decoder
ICLK output and back-end clock is XCLK from X port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (IDQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data outside the
scaling region
X
X
X
X
X
X
0
1
X
X
0
0
1
1
X
X
X
X
0
1
0
1
X
X
X
X
X
(2)
X
0
1
X
X
OUTPUT CLOCK PHASE CONTROL
CONTROL BITS 5 AND 4
XPCK1
XPCK0
XCLK default output phase, recommended value
XCLK output inverted
XCLK phase shifted by about 3 ns
XCLK output inverted and shifted by about 3 ns
0
0
1
1
0
1
0
1
X PORT I/O ENABLE
CONTROL BITS 2 TO 0
XRQT
X
(1)
X
X
X
0
1
XPE1
XPE0
X port output is disabled by software
X port output is enabled by software
X port output is enabled by pin XTRI at logic 0
X port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1 means
SAA7108E; SAA7109E is ready to receive data)
0
0
1
1
X
X
0
1
0
1
X
X