2004 Mar 16
170
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.2.4.2
Subaddresses 41H to 57H
Table 183
Line control register; LCR2 to LCR24 (41H to 57H); see Sections 9.2 and 9.4
18.2.4.3
Subaddress 58H
Table 184
Programmable framing code; slicer set 58H[7:0]; see Tables 44 and 183
18.2.4.4
Subaddress 59H
Table 185
Horizontal offset for slicer; slicer set 59H and 5BH
NAME
DESCRIPTION
FRAMING CODE
BITS 7 TO 4
(41H TO 57H)
BITS 3 TO 0
(41H TO 57H)
DT[3:0] 62H[3:0]
(FIELD 1)
DT[3:0] 62H[3:0]
(FIELD 2)
WST625
CC625
VPS
WSS
WST525
CC525
Test line
Intercast
General text teletext
VITC625
VITC525
Reserved
NABTS
Japtext
JFS
Active video
video component signal, active video
region (default)
teletext EuroWST, CCST
European Closed Caption
video programming service
wide screen signalling bits
US teletext (WST)
US Closed Caption (line 21)
video component signal, VBI region
raw data
27H
001
9951H
1E3C1FH
27H
001
programmable
programmable
programmable
programmable (A7H)
programmable
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
reserved
US NABTS
MOJI (Japanese)
Japanese format switch (L20/22)
FRAMING CODE FOR PROGRAMMABLE DATA TYPES
CONTROL BITS 7 TO 0
Default value
FC[7:0] = 40H
HORIZONTAL OFFSET
CONTROL BITS 5BH[2:0]
CONTROL BITS 59H[7:0]
Recommended value
HOFF[10:8] = 3H
HOFF[7:0] = 47H