參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 96/156頁
文件大小： 1782K
代理商： MC72000
96
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
RFEN—Receive FIFO Enable
This control bit enables the FIFO register for the receive section.
1 = Allows for eight samples (depending on the receive watermark set in the SFCSR) to be received
by the SSI (a ninth sample can be shifting in) before the RFF bit is set and an interrupt request
generated when enabled by the RIE bit.
0 = FIFO register is not used, and an interrupt request is generated when a single sample is received
by the SSI (interrupts need to be enabled).
TFEN—Transmit FIFO Enable
This control bit enables the FIFO register for the transmit section.
1 = A maximum of eight samples can be written to the STX (a ninth sample can be shifting out)
0 = FIFO register is not used.
RXDIR—Receive Clock Direction
This control bit selects the direction and source of the clock signal used to clock the receive shift register
(RXSR).
1 = Clock is generated internally and output to the SRCK pin.
0 = Internal clock generator is disconnected from the SRCK pin and an external clock source can
drive this pin to clock the RXSR.
Table 44 shows the clock pin configuration options.
NOTE:
RXDIR and SYN must both be high for the SSI to be in gated clock mode.
TXDIR—Transmit Clock Direction
This control bit selects the direction and source of the clock used to clock the TXSR.
1 = Clock is generated internally and is output to the STCK pin.
0 = Internal clock generator is disconnected from the STCK pin and an external clock source can
drive this pin to clock the TXSR.
Table 44 shows the clock configuration options.
SYN—Synchronous Mode
This control bit enables the synchronous mode of operation. In this mode, the transmit and receive
sections share a common clock pin and frame sync pin.
SYN and RXDIR control gated clock mode. The SSI is in gated clock mode when both SYN and
RXDIR are high.
Table 44. Clock Pin Configuration
SYN
RXDIR
TXDIR
RFDIR
TFDIR
SRFS
STFS
SRCK
STCK
Asynchronous Mode
0
0
0
0
Synchronous Mode
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
RFS in
RFS in
RFS out
RFS out
TFS in
TFS out
TFS in
TFS out
RCK in
RCK in
RCK out
RCK out
TCK in
TCK out
TCK in
TCK out
0
0
1
1
0
1
0
1
x
x
x
0
0
1
x
x
GPIO
GPIO
GPIO
GPIO
FS in
FS out
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
CK in
CK out
Gated in
Gated out
F
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