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參數(shù)資料
| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無線 |
| 文件頁數(shù)： | 75/156頁 |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
75
Configure the CSPI modules as master or slave before enabling them. The master CSPI should be enabled
before enabling the slave CSPI. The slave CSPI should be disabled before disabling the master CSPI. See
Section 7.3.7.3, “Control Register (CONTROLREG).” SPI_CK must be in the proper idle state before the
slave is enabled to prevent SPI_CK from appearing as a clock edge.
The following section describes the operation of the CSPI module.
Figure 43. CSPI Generic Timing
The CSPI does not consume any power when it is disabled.
7.3.8.2 Phase/Polarity Configurations
The serial peripheral interface master uses the SPI_CK signal to transfer data in and out of the shift register.
Data is clocked using any one of four programmable clock phase and polarity variations. In phase 0
operation, output data changes on the falling clock edges and input data is shifted in on rising edges. The
most significant bit (MSB) is output when the ARM7 loads the transmitted data. In phase 1 operation, output
data changes on the rising edges of the clock and input data is shifted in on falling edges. The MSB is output
on the first rising SPI_CK edge. Polarity inverts SPI_CK, but does not change the edge-triggered events that
are internal to the serial peripheral interface master. This flexibility allows the CSPI to operate with most
serial peripheral devices on the market.
7.3.8.3 Master Mode Operation
When the CSPI is configured as a master, in order to utilize the internal TXFIFO and RXFIFO, two auxiliary
output signals—SS_B and DATAREADY_B—are used for data transfer rate control. The user can also
program the sample period control register to a fixed data transfer rate.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the XCH bit. If SPIRDY[1:0] is set to zero and the PERIODREG[14:0] is set to zero,
then the first word in the TX FIFO immediately transfers to the shift register and begins shifting out on the
MOSI pin under the control of the serial clock.
The DRCTL[2:0] bits control the baud rate generator and determine the speed of the shift register. Through
the SPI_CK pin, the baud rate generator of the master also controls the shift register of the slave peripheral.
SPI_CK
MOSI
B
n
...
...
B
1
B
0
SPI_CK
SPI_CK
SPI_CK
(POL=1, PHA=1)
(POL=1, PHA=0)
(POL=0, PHA=1)
(POL=0, PHA=0)
MISO
B
n
...
...
B
1
B
0
B
n-1
B
n-2
B
n-1
B
n-3
B
n-3
B
n-2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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.
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| MC7220C-100M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 100M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 25M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 25M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 25M |
| MC7225C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-25C 25CORE 25M 制造商:pro-power 功能描述:MULTICORE, 25, 7/0.2MM, 25M, BLACK 制造商:pro-power 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M 制造商:PRIVATE LABEL 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M, Reel Length (Imperial):82ft, Reel Length (Metri |
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