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參數資料
| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍牙無線 |
| 文件頁數： | 50/156頁 |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
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50
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
— Controlled recovery and clock restarts
Watchdog (COP) surveillance
Clock control and generation
Software-initiated system reset
7.1.2 Modes of Operation
Power Up
After POR the CRM module will delay the release of the 32 kHz oscillator clock to the rest of the
system until the oscillator has time to stabilize. After the ARM core begins operating, it will control
the switch over to the REFCLK signal.
Normal Operation
The MC72000 system clock operates on the 12-32 MHz reference clock (REFCLK) from the radio.
Sleep Operation
During sleep mode, the high frequency reference clock from the radio will be turned off, and only
the 32 kHz clock will be used to clock the vital parts of the CRM module. Sleep mode is initiated
by setting the PDE bit in the Wake Up Control register. Sleep mode can be ended by either the
internal wake up timer or one of the four external wake up interrupts.
7.1.2.1 External Clock Control Register
The CRM module generates two derivatives of REFCLK. The frequencies of these clocks are
programmable in the range of ~500 kHz to REFCLK. The resulting clocks are named CLK0 (fractional
divided), and CLK1 (integer divided) on the output pads. These clocks can be used to feed external devices
such as a USB, CODEC, or whatever the final system application needs. The duty cycle of CLK0 and
CLK1 cannot be expected to be 50/50 because of the nature of REFCLK from the RF IC as well as
additional changes introduced by the clock divider circuitry. Any external device using CLK0 or CLK1
should be held in reset whenever the frequency of these clocks is changed because the periods may be
unstable for some time immediately after the change request. Because the external clocks operate
independently, there is no implied phase relationship between CLK0 and CLK1 if their divisors are the
same or integer multiples. These clocks will be stopped in sleep mode because they are derivatives of
REFCLK which is also stopped in sleep mode.
CLK1_DIV[3:0] — Clock1 Divisor
The CLK1_CNTRL register controls the integer division of the REFCLK to generate the CLK1 output
signal. The CLK1 output will be low when CLK1_DIV is disabled.
Table 25. CLK1_DIV Values
Value
Divisor
@32 Mhz refclk
Duty Cycle
000
001
010
011
100
101
110
111
CLK1 Disabled (Low)
divide 1
divide 2
divide 4
divide 8
divide 16
divide 32
divide 64
NA
32 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
REFCLK dependent
50/50
50/50
50/50
50/50
50/50
50/50
F
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