參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 67/156頁
文件大?。?/td> 1782K
代理商： MC72000
MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
67
7.3.7 Register Descriptions
7.3.7.1 RX Data Register (RXDATAREG)
Figure 36. RX Data Register (RXDATAREG)
RXDATAREG is 32-bit read-only register. The lower 16 bits hold the top of the 8 x 16 RXFIFO received
from an external CSPI device during a data transaction. The upper 16 bits are reserved bits and are always
read as 0. Bits beyond the current setting of the BITCOUNT register are invalid and should be masked by
the user software.
DATA[15:0] — CSPI Data in the RXFIFO
DATA has no meaning if the RR bit in the interrupt control/status register is clear.
7.3.7.2 TX Data Register (TXDATAREG)
Figure 37. TX Data Register (TXDATAREG)
TXDATAREG is a 32-bit write-only data register. The lower 16 bits is the top of the 8 x 16 TXFIFO.
Writing to TXFIFO is permitted as long as it is not full, even though the XCH bit is set, that is, the user could
write to TXFIFO during CSPI data exchange process. Writes to this register are ignored while the SPIEN
bit is clear. The upper 16 bits are reserved bits and are always read as 0.
DATA[15:0] — CSPI data to be loaded to the 8x16 TXFIFO
In master or slave mode, a maximum of eight data words are loaded. Data writes to this register can be
either 8-bit or 16-bit size. The number of bits to be shifted out of the 16-bit transmit FIFO element is
determined by the BIT COUNT value in the control register. The unused MSBs are don’t cares. For
example, to transfer 10-bit data, a 16-bit word is written to this register and the six MSBs are don’t cared
and are not shifted out. In slave mode, if no data is loaded in the TXFIFO, 0s are shifted out on the TXD
signal.
Register address: BASE + 0x00
31
30
29
28
27
26
25
24
Reserved
0
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Data[15:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Register address: Base + 0x04
31
30
29
28
27
26
25
24
Reserved
0
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
if SPIEN == 1, Data[15:0], else 0x0000
Data[15:0]
0
0
0
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
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