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| 型號(hào)： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無線 |
| 文件頁數(shù)： | 115/156頁 |
| 文件大小： | 1782K |
| 代理商： | MC72000 |
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
115
An interrupt can occur after the reception of each data word or the programmer can poll the RDR flag. The
SSI program response can be one of the following:
Read SRX and use the data.
Read SRX and ignore the data.
Do nothing—the receiver overrun exception occurs at the end of the current time slot.
7.4.6.1.3
Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the SSI may be synchronous or asynchronous. During asynchronous
operation, the transmitter and receiver have their own separate clock and sync signals. When operating in
synchronous mode, the transmitter and receiver use common clock and synchronization signals, as specified
by the transmitter configuration. The SYN bit in SCR2 selects synchronous or asynchronous operation.
Since the SSI is designed to operate either synchronously or asynchronously, separate receive and transmit
interrupts are provided. During synchronous operation, the receiver and transmitter operate in lock step with
each other and the software designer may want to reduce overhead by eliminating either the receive or
transmit interrupts, driving both channels from the same set of interrupts. If this decision is made, the
software designer needs to be aware of the specific timing of the receive and transmit interrupts since the
interrupts are not generated at the exact same point in the frame timing, as shown in Figure 76. If it is desired
to run off a single set of interrupts, the TX interrupts should be used. If RX interrupts are used, there may
be timing problems with the transmit data since this interrupt occurs a half-bit time before the transmit data
is used by the hardware.
Figure 76. Synchronous Mode Interrupt Timing
6
RDR
status flag
and
receive
interrupt
This flag is set for each word clock (time-slot) to indicate that data is available to
be processed. The software must keep track of the time-slots as they occur so it
knows which data to keep.
If the receive interrupts are enabled (RIE=1), an interrupt will be generated when
this status flag is set. The software reads the SRX register to clear the interrupt
(see Section 7.4.9.2, “Description of Interrupt Operation,” for a complete
description of interrupt processing).
Table 57. Notes for Receive Timing in Figure 75 (Continued)
Note
Source
Signal
Destination
Signal
Description
Continuous STCK
STFS
STX register
TDE status bit/interrupt
RDR status bit/interrupt
Valid
Indefinite transition depends on SW interrupt processing
Invalid
TX
RX
TX
RX
F
Freescale Semiconductor, Inc.
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