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參數(shù)資料
| 型號(hào)： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無(wú)線 |
| 文件頁(yè)數(shù)： | 92/156頁(yè) |
| 文件大小： | 1782K |
| 代理商： | MC72000 |
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92
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
TUE—Transmitter Underrun Error
This flag bit is set when the TXSR is empty (no data to be transmitted), as indicated by the TDE bit
being set, and a transmit time slot occurs. When a transmit underrun error occurs, the previously sent
data is retransmitted.
A transmit time slot in the normal mode occurs when the frame sync is asserted. In network mode, each
time slot requires data transmission and, therefore, may cause a TUE error.
The TUE bit does not cause any interrupts. However, the TUE bit does cause a change in the interrupt
vector used for transmit interrupts so that a different interrupt handler can be used for a transmit
underrun condition. If a transmit interrupt occurs with the TUE bit set, the transmit data with exception
status interrupt is generated. If a transmit interrupt occurs with the TUE bit cleared, the transmit data
interrupt is generated.
The TUE bit is cleared by power-on or SSI reset. The TUE bit is also cleared by reading the SCSR with
the TUE bit set, followed by writing to the STX register or to the STSR.
TFS—Transmit Frame Sync
When set, this flag bit indicates that a frame sync occurred during transmission of the last word written
to the STX register. As shown in Figure 60b, data written to the STX register during the time slot when
the TFS bit is set is transmitted during the second time slot (in network mode) or in the next first time
slot (in normal mode). In network mode, the TFS bit is set during transmission of the first slot of the
frame. It is then cleared when starting transmission of the next slot. The TFS bit is cleared by power-on
or SSI reset.
RFS—Receive Frame Sync
When set, this flag bit indicates that a frame sync occurred during receiving of the next word into the
SRX register, as shown in Figure 60c. In network mode, the RFS bit is set while the first slot of the
frame is being received. It is cleared when the next slot of the frame begins to be received. The RFS bit
is cleared by power-on or SSI reset.
RFF—Receive FIFO Full
This flag bit is set when the receive section is programmed with the receive FIFO enabled, and the data
level in the RXFIFO reaches the selected receive FIFO watermark (RFWM) threshold. When set, RFF
indicates that data can be read via the SRX register.
NOTE:
An interrupt is only generated if both the RFF and RIE bits are set if
RXFIFO is enabled.
The RFF bit is cleared in normal operation by reading the SRX register. The RFF is also cleared by
power-on reset or disabling the SSI.
When RXFIFO is completely full, all further received data is ignored until data is read.
TFE—Transmit FIFO Empty
This flag bit is set when the transmit section is programmed with the TXFIFO enabled and the data level
in the TXFIFO falls below the selected transmit FIFO watermark (TFWM) threshold. When set, the
TFE bit indicates that data can be written to the TXFIFO register. The TFE bit is cleared by writing data
to the STX register until the TXFIFO data content level reaches the watermark level.
NOTE:
An interrupt is generated only if both the TFE and the TIE bits are set if
transmit FIFO is enabled.
F
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