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參數(shù)資料
| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無線 |
| 文件頁數(shù)： | 117/156頁 |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
117
7.4.6.1.4.2
Operation with RSM Register
The RSM register is included in the design so that interrupt overhead can be reduced. If all bits of the RSM
register are set, the SSI receiver will continue to operate as previously described. The RSM register is used
to automatically discard data from selected time-slots. This is accomplished by writing the RSM with 0 in
the selected time-slot bit location. This means no data is transferred from the receive shift register (RXSR)
on the 0 time-slots, no status flags change, and no interrupts are generated.
The receiver timing, using the RSM registers, for an 8-bit word with continuous clock, FIFO disabled, five
words per frame sync, in network mode is shown in Figure 78. The explanatory notes for the receive portion
of the figure are shown in Table 59.
NOTE:
In this example there are only two receive interrupts per frame instead of
five as in the previous example where the RSM register is not used.
Table 58. Notes for Transmit Timing with Mask Register in Figure 77
Note
Source
Signal
Destination
Signal
Description
1
Example of a 5 time-slot frame, transmitting in time-slots 0 and 3.
Example with word-length frame sync and standard timing (TFSI=0, TFSL=0,
TEFS=0). Frame timing begins with the rising edge of STFS.
This flag is set at the beginning of each word (for enabled time-slots) to indicate
that the STX data has been used and another data word should be supplied by the
software. If the transmit interrupt is enabled, the processor is interrupted to request
the data. The flag (and interrupt) are cleared when data is written to either the STX
or STSR registers (see Section 7.4.9.2, “Description of Interrupt Operation,” for a
complete description of interrupt processing).
On each word clock boundary, a decision is made concerning what to transmit on
the next time-slot. If the TSMn register bit is a 0 for the next time-slot, the STXD
pin is tri-stated and the time-slot is ignored.
If the TSMn register bit is a 1 for the next time-slot, the contents of the STX register
are transferred to the TXSR register and this data is shifted out. If the STX register
has not been written in the previous time-slot, the previous data is reused.
2
STFS
3
TDE status
flag and
interrupt
4
STX\STSR
register
TXSR
register
NOTE:
If the STSR is written instead of the STX, the
STXD pin is tri-stated as documented in
Section 7.4.6.1.2, “Network Mode.”
If neither of these registers were written in the previous time-slot (where TSMn=1),
the TUE status bit will be set and the hardware will operate as if the STX register
had been written. The STXD pin will be enabled and the contents of the STX will
be transmitted again. Note that this may lead to drive conflicts on the transmit data
line, if another device is transmitting data during this time-slot.
On active time-slots, the TXSR register contents are shifted out on the STXD pin,
one bit per rising edge of STCK.
On inactive time-slots, the STXD pin is tri-stated so it can be driven by another
device.
5
TXSR
register
STXD pin
F
Freescale Semiconductor, Inc.
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| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 25M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 25M |
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