
Package Pinout
MOTOROLA
MC72000
Advance Information Data Sheet
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23
TRST_B
This active low Schmitt trigger input pin provides an asynchronously reset signal to all TAP
controllers to initialize the test controller. Leave open or pull-down if JTAG is unused.
TMS
The test mode select input pin is used to sequence all TAP controllers. The TAP control module
and the TTS device port determine the TAP sequenced. TMS is sampled on the rising edge of
TCK. Leave open or pull-up if JTAG is unused.
TCK
The test clock input pin is used to synchronize the JTAG test logic. It provides the clock to
synchronize the test logic and shift serial data to and from all TAP controllers. Leave open if JTAG
is unused.
RTCK
The return test clock output pin returns the synchronization test clock to ARM development tools to
be entered from the serial debug input line.
TTS
The test tap select input pin directly controls the multiplexing logic to select between the chip TAP
and the core TAP. A logic 1 applied to the tap select input will select the chip TAP. Leave open if
JTAG is unused.
MODE1
Test/boot mode select pins. In order to support a flexible development system, the system must be
able to boot from different memories during system reset and power-up. This pin can select two of
the four different memory maps, as MODE0 is hardwired internally. All the different boot modes
start reading data at address 0x0000_0000, since this is where the ARM7 reset vector is located.
RESET_BB
The reset in pin is an active low Schmitt trigger input that provides reset to the internal circuitry. The
RESET input will be qualified as valid if it will be asserted for at least three CLK cycles.
Bluetooth Signals
REFCTRL
The reference control pin is a dedicated output from the clock reset module (CRM) which enables/
disables the reference clock.
SSI and UART Signals
SSI_SCK
/GPIO_B0/GPIO_B3/BT_TP0/BT_TP3
SSI_SCK
Normal mode
The serial transmit clock signal is used by the transmitter and can
be either continuous or gated. The pin is normally used in
synchronous mode. Two signals are internally connected in the chip
to this pin. Use precautions when configuring these two signals, as
the two internal signals must be configured to comply with each
other.
GPIO_B0/
GPIO_B3
Alternate Function 1 (GPIO)
GPIO_0 or GPIO_3 on Port B. Two signals are internally connected
in the chip to this pin. Use precautions when configuring these two
signals, as the two internal signals must be configured to comply
with each other.
BT_TP0/
BT_TP3
Alternate Function 2
Bluetooth test port
signal.
Two signals are internally connected in
the chip to this pin. Use precautions when configuring these two
signals, as the two internal signals must be configured to comply
with each other.
SSI_FS
/GPIO_B1/GPIO_B4/BT_TP1/BT_TP4
Table 15. Pin Descriptions (Continued)
F
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