參數(shù)資料
型號: MC72000
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Integrated Bluetooth Radio
中文描述: 集成藍牙無線
文件頁數(shù): 66/156頁
文件大?。?/td> 1782K
代理商: MC72000
66
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.3.5.4 SS_B — SPI Slave Select
The SS_B pin has various functions depending on the current state of the CSPI CONTROLREG. For a CSPI
configured as a slave, the SS_B pin is used to select a slave. When a CSPI is configured as a slave, the SS_B
pin is always configured as an input. It cannot be used as a general purpose I/O.
When a CSPI is configured as a master, for PHA = 1, the SS_B is used to define the start of a new word
transmission. However, it can remain low between word transmissions for the PHA = 0 format.
When enabled in the GPIO function select register, the CSPI controls data direction of the SS_B pin
regardless of the state of the GPIO data direction register of the shared I/O port.
7.3.5.5 DATAREADY_B — SPI Data Ready
The DATAREADY_B pin is used in master mode to allow a slave device to signal the master that the slave
is ready to deliver some new data to the master.
When enabled in the GPIO function select register, the CSPI controls data direction of the
DATAREADY_B pin regardless of the state of the GPIO data direction register of the shared I/O port.
7.3.6 Memory Map and Registers
Table 29 shows the CSPI memory map. There are 8 user programmable registers which are 16 bits. All
registers are aligned to the 32-bit word address width and always return zeros in the upper 16 bits whenever
read. The AIPI can be set to enable the CRM for either 32- or 16- bit transfers. All registers are byte and
halfword accessible. The base address of the CSPI0 and CSPI1 modules on the MC72000 is 32’h8000_8000
and 32’h8000_9000.
The following sections provide detailed descriptions of each of the CSPI registers. All readable registers
will return 0x0 after reset unless otherwise specifically stated. All reserved bits are read as zero and should
be written with zero for future compatibility.
Table 29. CSPI Memory Map
Address
Use
Access
Base + 0x00
Base + 0x04
Base + 0x08
Base + 0x0C
Base + 0x10
Base + 0x14
Base + 0x18
Base + 0x1c
RX Data Register (RXDATAREG)
TX Data Register (TXDATAREG)
Control Register (CONTROLREG)
Interrupt Control/Status Register (INTREG)
CSPI Test Register (TESTREG)
CSPI Sample Period Control Register (PERIODREG)
Reserved
CSPI Soft Reset Register (RESETREG)
R
R/W
R/W
R/W
R/W
R/W
N/A
R/W
F
For More Information On This Product,
n
.
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