參數(shù)資料
型號: MC72000
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Integrated Bluetooth Radio
中文描述: 集成藍牙無線
文件頁數(shù): 86/156頁
文件大?。?/td> 1782K
代理商: MC72000
86
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Figure 54. SRX Register Diagram
7.4.5.2.5
SSI Receive FIFO Register (RXFIFO)
The RXFIFO is a 7 x 16-bit FIFO register used to buffer samples received in the SSI receive data register
(SXR). The receive FIFO is enabled by setting the RFEN bit of the SCR2 control register. Received data is
then held in the FIFO if the data in the SRX has not yet been read.
If the receive interrupt is enabled, it is asserted whenever the SRX is full and the data level in the SSI receive
FIFO reaches the selected threshold. If the receive FIFO feature is not enabled, this register is bypassed and
the receive shift register (RXSR) data is automatically transferred into the SRX.
7.4.5.2.6
SSI Receive Shift Register (RXSR)
RXSR is a 16-bit shift register that receives incoming data from the serial receive data SRXD pin. When a
continuous clock is used, data is shifted in by the selected (internal/external) bit clock when the associated
(internal/external) frame sync is asserted. When a gated clock is used, data is shifted in by the selected
(internal/external) gated clock. Data is assumed to be received MSB first if the SHFD bit of the SCR2 is
cleared. If this bit is set, the data is received LSB first. Data is transferred to the SSI receive data register
(SRX) or receive FIFO (if the receive FIFO is enabled and SRX is full) after 8, 10, 12, or 16 bits have been
shifted in depending on the WL[1:0] control bits. For receiving 8, 10, or 12 bits data, LSB bits are set to zero.
See Figure 55 and Figure 56 for more information.
Figure 55. Receive Data Path (RSHFD=0)
Base + 0x02
15
14
13
12
high byte
11
10
9
8
7
6
5
4
low byte
3
2
1
0
R
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
SRX
15
0
16 bits
8
7
8 bits
12 bits
10 bits
15
0
RXSR
SRXD
F
For More Information On This Product,
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