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參數(shù)資料
| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍牙無線 |
| 文件頁數(shù)： | 116/156頁 |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
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116
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.4.6.1.4
Network Mode with Mask Registers Implemented
In order to reduce interrupt overhead, a number of enhancements can be made to the SSI module. The
enhancements incorporate the mask registers (TSM and RSM) and the frame status register (SFSR).
Figure 77 and Figure 78 show sample timing of network mode transfers, using the mask registers. These
figures duplicate the frame structure of Figure 74 to show the reduced amount of interrupt processing
required. The numbered circles and arrows in the figures identify discussion notes which are contained in
Table 58 and Table 59.
7.4.6.1.4.1
Operation with TSM Register
The TSM register is included in the design so that interrupt overhead can be reduced. If all bits of the TSM
register are set, the SSI transmitter will continue to operate as previously described. The TSM register is
used to disable the STXD pin on specific time-slots. This is accomplished by writing the TSM with 0 in the
time-slot bit location. Disabling a time-slot in this manner causes the time-slot to be ignored by the SSI. This
means no data is transferred to the transmit shift register (TXSR) and no interrupts are generated for this
time-slot.
The transmitter timing, using the TSM registers, for an 8-bit word with continuous clock, FIFO disabled,
five words per frame sync, in network mode is shown in Figure 77. The explanatory notes for the transmit
portion of the figure are shown in Table 58.
NOTE:
In this example there are only two transmit interrupts per frame instead of
five as in the previous example where the TSM register is not used.
Figure 77. Network Mode Transmit Timing with Mask Register
TS 0
TS 1
TS 2
TS 3
TS 4
TS 0
TSM[0]
TSM[1]
TSM[2]
TSM[3]
TSM[4]
TSM[0]
time-slot
Continuous STCK
internal word clock
STFS
TSMn bits usage
TDE status bit/interrupt
STX register
TXSR register
STXD
2
5
1
4
Valid
Indefinite transition depends on SW interrupt processing
Invalid
3
4
F
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