參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 104/156頁
文件大?。?/td> 1782K
代理商： MC72000
104
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Figure 69. RSMB Register Diagram
The receive slot mask registers are two 16-bit read/write registers. In network mode, these registers are used
by the receiver to determine which action to take in the current time slot. Depending on the setting of the
bits, the receiver either ignores the receiver data signal(s) or receives a data word and generates the
appropriate receive status.
RSMA and RSMB can be viewed as one 32-bit register, RSM. Bit n in RSM (RSMn) is an enable/
disable control bit for time slot number N.
1 = Receive sequence proceeds normally.
Data is received during slot number N, and the RDR flag is set.
0 = Data is not transferred from the receive shift register (RXSR) to the receive data register (SRX)
and, therefore, the RDR and ROE flags are not set.
During a disabled slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled
slots.
When the bits in the RSM are set, their settings affect the next frame reception. The frame currently being
received is not affected by the new RSM setting. If the RSM is read, it shows the current setting.
After a hardware RESET signal or executing a DSP software RESET instruction, the RSM register is reset
to $FFFFFFFF; that value enables all 32 time slots for data reception. The receive DC setting determines
how many of these control bits are actually used.
7.4.5.3.1
SSI Frame Status Register (SFSR)
This register can be read at any time to determine the current time slot of the frame. This register is only
useful for network mode.
Figure 70. SFSR Register Diagram
RTSCNT — Receive Time-Slot Count
This read-only bit field indicates the current time-slot number within the receive frame. This count will
indicate the specific bit of the RSM that is currently active. The value of this field will change with the
receive word count clock (see Figure 78).
Base + 0x1A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
RSMA[31:16]
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
Base + 0x1C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
RTSCNT
TTSCNT
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved (write as 0)
F
For More Information On This Product,
n
.
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