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| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無線 |
| 文件頁數(shù)： | 126/156頁 |
| 文件大小： | 1782K |
| 代理商： | MC72000 |
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126
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Bluetooth Baseband Functionality Overview
7.4.10.1 Frame Sync/Clock Phasing
When using an external bit-wide frame sync, the transmit frame sync should be asserted when the clock is
asserted and should remain asserted for a full clock period. The timing of the trailing edge of STFS is no
longer critical with respect to the rising edge of STCK. This is shown in Figure 87.
Figure 87. SSI Frame Sync versus Clock Timing Diagram
7.4.10.2 External Frame Sync Setup
When using external frame syncs, there must be at least four clocks after enabling the transmitter/receiver
and before the first frame sync.
7.4.10.3 Max External Clock Rate
The maximum allowable rate for an external clock source is 1/4 of the peripheral clock, or up to 2 Mbits/s.
8 Bluetooth Baseband Functionality Overview
This section describes the features of the Bluetooth baseband stack, which is included in the MC72000.
The baseband runs on the ARM7 microcontroller and features highly advanced third generation link
control (LC), link manager (LM), and human-computer interface (HCI) layers fully compliant with the
Bluetooth v1.1 specification.
The baseband stack is specifically designed with complex scenarios in mind, and is capable of handling
concurrent execution of multiple HCI, LM, and LC procedures. This means that the stack is well suited
even for advanced scenarios involving full 7 slave piconet situations as well as scatternet operation. The
stack also features state-of-the-art Bluetooth audio and includes all Bluetooth v1.1 supported air coding
formats.
In order to ensure high quality and stability, the stack has been thoroughly tested by an independent test
house. Furthermore, the baseband is firmware upgradeable through a ROM patching system allowing
firmware patches resident in an attached EEPROM to be applied.
149
SRD hold after STCK low
5
CPmax-20
ns
1.
non-inverted serial clock polarity and a non-inverted frame sync. If the polarity of the clock and/or the
frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK and/or the
frame sync FSR/FST in the tables and in the figures.
2.
bl = bit length; wl = word length
3.
CPmax = clock period max for system
Based on SYSCLK of 24 MHz (from MC72000 BT radio). All the timings for the SSI are given for a
Table 63. SSI Timing (Continued)
No.
Characteristic
Min
Max
Unit
STCK
STFS
F
For More Information On This Product,
n
.
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| MC7220C-100M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 100M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 25M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 25M |
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| MC7225C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-25C 25CORE 25M 制造商:pro-power 功能描述:MULTICORE, 25, 7/0.2MM, 25M, BLACK 制造商:pro-power 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M 制造商:PRIVATE LABEL 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M, Reel Length (Imperial):82ft, Reel Length (Metri |
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