參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 102/156頁
文件大?。?/td> 1782K
代理商： MC72000
102
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.4.5.2.13
SSI Option Register (SOR)
Figure 65. SOR Register Diagram
RFDIR—Receive Frame Direction
This control bit selects the direction and source of the receive frame sync signal.
1 = Receive frame sync
is generated internally and output to the SRFS pin.
0 = Receive frame sync is external, meaning that the receive frame sync is supplied from an external
source.
TFDIR—Transmit Frame Direction
This control bit selects the direction and source of the transmit frame sync signal.
1 = Transmit frame sync
is generated internally and output to the STFS pin.
0 = Transmit frame sync is external, meaning that the transmit frame sync is supplied from an
external source.
INIT—Initialize State Machine
This bit is used to initialize the state machine to reset state.
1 = Reset the TX and RX state machines.
Setting this bit must be followed by a write of zero before the state machine with operate.
0 = State machine is allowed to operate.
WAIT[1:0]—Wait State
This bit field controls the number of wait states to be added to the transaction between the CPU and SSI.
The MC72000 does not use wait states and as such these should always be written 0.
SYNRST—Frame Sync Reset
1 = Resets the accumulation of data in SRX and RXFIFO on frame synchronization.
0 = Data must be read to be cleared from the registers.
7.4.5.2.14
Transmit Slot Mask Registers (TSMA, TSMB)
Figure 66. TSMA Register Diagram
Base + 0x12
15
14
13
12
11
10
9
8
7
Reserved
(write as 0)
0
6
5
4
3
2
1
0
R
W
RFDIR TFDIR
INIT
WAIT[1:0]
SYN
RST
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Base + 0x14
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
TSMA[15:0]
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
F
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