參數(shù)資料
型號(hào)： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 114/156頁
文件大小： 1782K
代理商： MC72000
114
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
3. Enable RXFIFO (RFEN=1) and configure receive watermark (RFWM=n) if RXFIFO is
used.
4. Enable receive interrupts.
5. Set the RE bit (RE = 1) to enable the receiver operation on the next frame sync boundary.
The receiver timing for an 8-bit word with continuous clock, FIFO disabled, five words per frame sync, in
network mode is shown in Figure 75. The explanatory notes for the receive portion of the figure are shown
in Table 57.
Figure 75. Network Mode Receive Timing
Table 57. Notes for Receive Timing in Figure 75
Note
Source
Signal
Destination
Signal
Description
1
Example of a 5 time-slot frame, receiving data from time-slots 0 and 2. Note that
the receive hardware will obtain data on the SRXD pin every bit time. The software
must determine which data belongs to each time-slot and discard the unwanted
time-slot data.
The figure shows the transmit and receive timing as the same, although this is not
the general case.
Example with bit-length frame sync and standard timing (RFSI=0, RFSL=1,
REFS=0). Frame timing begins with the rising edge of SRFS.
Data on the SRXD pin is sampled on the falling edge of SRCK and shifted into the
RXSR register.
At the word clock, the data in the RXSR register is transferred to the SRX register.
2
SRCK
3
SRFS
4
SRXD
RXSR
register
5
RXSR
register
SRX register
TS 0
TS 1
TS 2
TS 3
TS 4
TS 0
time-slot
Continuous SRCK
internal word clock
SRFS
RFS bit of SCSR register
SRXD
RXSR register
SRX register
RDR status bit/interrupt
5
Valid
Indefinite transition depends on SW interrupt processing
Invalid
6
8
9
10
11
F
For More Information On This Product,
n
.
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