參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 108/156頁
文件大?。?/td> 1782K
代理商： MC72000
108
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Figure 72. Normal Mode Receive Timing—Continuous Clock (WL=8-bit words, DC=1)
Table 53. Normal Mode Receive Operations
Step
RXFIFO Disabled
(See Figure 72)
RXFIFO Enabled
(No Figure Available
1
Leading edge of frame sync occurs on the
SRFS pin
Falling edge of receive clock occurs on the
SRCK pin and the next bit of data is shifted into
the RXSR register
When WL bits (see Section 7.4.5.2.7, “SSI
Transmit and Receive Control Registers
(STXCR, SRXCR)”) have been received RXSR
contents are transferred to the SRX register on
the next falling edge of the receive clock
Note: The SRX register is actually loaded during
the middle of the last receive bit.
Flag status update
2
3
4
The RDR bit is set
The RFF bit is set if the level of data in the
RXFIFO rises above the watermark level
Receive interrupt occurs when RFF set
5
If the RIE bit is set, enabling receive interrupts,
then:
(Other options for processing the data transfer
is either polling or DMA transfers.)
Receive over-run (setting the ROE bit of the
SCSR register) is prevented by
1
:
Receive interrupt occurs
when RDR set
6
1.See the description of the ROE bit in
Section 7.4.5.2.8, “SSI Control/Status Register (SCSR)”
for a description of what
happens when the ROE bit is set.
2.The frame sync must not occur earlier than what is configured in the SRXCR as documented in Section 7.4.5.2.7, “SSI
Transmit and Receive Control Registers (STXCR, SRXCR).”
Data is read from the SRX
before the RXSR tries to
write new transmit data at
the next frame sync
Data is read from the SRX before the
RXSR tries to provide more data to a full
RXFIFO (it can take several frame times
to fill the RXFIFO)
7 Repeat at step 1 on the next frame sync
2
Continuous SRCK
SRFS
SRXD
RXSR register
SRX register
RDR status bit/interrupt
Valid
Indefinite transition depends on SW interrupt processing
Invalid
1
2
3
4
F
For More Information On This Product,
n
.
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