參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 106/156頁
文件大?。?/td> 1782K
代理商： MC72000
106
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
If normal mode is configured to provide more than one time slot per frame, data is transmitted only in the
first time slot. No data is transmitted in subsequent time slots. Figure 71 and Figure 72 show sample timing
of normal mode transfers.
7.4.6.1.1.1
Normal Mode Transmit
The conditions for data transmission from the SSI in normal mode are as follows:
1. Set the SCSR, STXCR, SCR2, and SOR registers to select normal mode operation, define
the transmit clock, transmit frame sync, and frame structure required for proper system
operation.
2. Enable SSI enabled (SSIEN = 1).
3. Enable TXFIFO (TFEN=1) and configure the transmit watermark (TFWM=n) if this
TXFIFO is used.
4. Write data to transmit data register (STX).
5. Enable transmit interrupts.
6. Set the TE bit (TE = 1) to enable the transmitter on the next frame sync boundary.
Figure 71 and Table 52 describe the functions performed during transmit operation in this mode.
Figure 71. Normal Mode Transmit Timing—Continuous Clock (WL=8-bit words, DC=1)
Table 52. Normal Mode Transmit Operations
Step
TXFIFO Disabled
(See Figure 71)
TXFIFO Enabled
(No Figure Available)
1
Rising edge of STFS
Note: A word length frame sync is shown. This
only works if DC>0.
2 Data transferred to TXSR
STXD output pin is enabled
1
and the first bit of
the TXSR register appears on the output
Flag status update
From STX
From TXFIFO
3
4
The TDE bit is set
The TFE bit is set if the level of data in the
TXFIFO falls below the watermark level
Valid
Indefinite transition depends on SW interrupt processing
Invalid
Continuous STCK
STFS
STX register
TDE status bit/interrupt
TXSR register
STXD
2
4
6
7
1
F
For More Information On This Product,
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