參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 58/156頁
文件大小： 1782K
代理商： MC72000
58
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
NOTE:
Bits[7:6] are cleared when the respective condition allows it. Status
bits[5:0] are cleared when the register is read.
TXRdy—Transmitter is Causing an Interrupt
1 = Interrupt pending
0 = No interrupt
RXRDY—Receiver is Causing an Interrupt
1 = Interrupt pending
0 = No interrupt
RUE—RX FIFO Underrun Error
This read-only bit indicates, while HIGH, that the RXFIFO underrun error occurred. This occurs when
software reads more from the FIFO than is actually present. This bit is updated and valid for each
received character. This bit is set for the last character written to the FIFO indicating that all characters
following this character will be ignored if a write is not performed by software. The RUE bit is cleared
by UART reset or by reading the USTAT register.
1 = Error occurred
0 = No error
ROE—RX FIFO Overrun Error
This read-only bit indicates, while HIGH, that the RXFIFO ignored data to prevent overwriting the data
in the FIFO. Under normal circumstances, this bit should never be set. It indicates that the user’s
software is not keeping up with the incoming data rate. This bit is updated and valid for each received
character. This bit is set for the last character written to the FIFO indicating that all characters following
this character will be ignored if a read is not performed by software. The ROE bit is cleared by UART
reset or by reading the USTAT register.
1 = Error occurred
0 = No error
TOE—TX FIFO Overrun Error
This flag bit is set when the UDATA register is filled and ready to transfer to the TXFIFO register and
the register is already full. This error occurs when the software writes more data than is room for in the
FIFO. The transmit data is not transferred in this case. A transmit overrun error does not cause any
interrupts. The TOE bit is cleared by UART reset or by reading the USTAT register.
1 = Error occurred
0 = No error
USTATBase + $004
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
22
0
21
0
20
0
19
0
18
0
17
0
16
0
R
W
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
TXRD
Y
RXRD
Y
RUE
ROE
TOE
FE
PE
SE
W
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= writes have no effect and terminate without transfer error exception
F
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