參數(shù)資料
型號: MC72000
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Integrated Bluetooth Radio
中文描述: 集成藍牙無線
文件頁數(shù): 69/156頁
文件大?。?/td> 1782K
代理商: MC72000
MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
69
SPIEN — CSPI Module Enable
This bit enables the serial peripheral interface. This bit must be asserted before an exchange is initiated.
Writing a 0 to this bit clears the RX and TX FIFO data and control registers along with the internal
counters and state machine. Changing any of the other CONTROLREG bits, except XCH, when SPIEN
is set is not allowed and may cause the CSPI to enter an invalid state.
1 = The serial peripheral interface is enabled
0 = The serial peripheral interface is disabled
XCH—Exchange
In master mode, writing a 1 to this bit triggers a data exchange. This bit remains set while either the
exchange is in progress, or the CSPI is waiting for an active DATAREADY_B input when SPIRDY is
enabled. This bit is cleared automatically when all data in the TXFIFO and shift register is shifted out.
In slave mode, this bit must be clear.
1 = Initiates exchange (write) or busy (read)
0 = Idle
SSPOL — SS_B Polarity Select
This bit selects the polarity of SS_B signal in both master and slave mode.
1 = Active high
0 = Active low
SSCTL — SS_B Wave Form Select
This bit selects the output waveform for SS_B signal in master mode.
1 = Insert pulse between CSPI bursts
0 = SS_B stays low between CSPI bursts
This bit controls RXFIFO advancement in slave mode.
1 = RXFIFO is advanced by SS_B rising edge
0 = RXFIFO is advanced by BITCOUNT[3:0]
PHA—Phase
This bit controls the clock/data phase relationship.
1 = Phase 1 operation
0 = Phase 0 operation
POL—Polarity
This bit controls the polarity of the SCLK signal.
1 = Active low polarity (1 = idle)
0 = Active high polarity (0 = idle)
BITCOUNT[3:0]—Bit Count
This bit field selects the length of the transfer. A maximum of 16 bits can be transferred.
In master mode a 16-bit data word is loaded from the TXFIFO to the shift register and only the least n
bits (n = BITCOUNT) are shifted out. The next 16-bit word is then loaded to shift register.
In slave mode when the SSCTL bit is 0 this field controls the number of bits received as a data word
loaded to the RXFIFO. When the SSCTL bit is 1, this field is a don’t care.
Table 32 shows the BITCOUNT[3:0] encoding.
Table 32. BITCOUNT[3:0] Encoding
BITCOUNT[3:0]
Function
0000
1-bit transfer
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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