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參數(shù)資料
| 型號(hào)： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無線 |
| 文件頁數(shù)： | 55/156頁 |
| 文件大?。?/td> | 1782K |
| 代理商： | MC72000 |
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
55
be asserted as well and an interrupt is posted (if MRXR = 0). The RXRDY interrupt flag is cleared when
the RXFIFO empties below the programmed trigger level.
7.2.4.5 Receiving a Break Condition
Receiving a break condition is detecting all zeros including a zero during the stop bit bit time. When a break
condition is detected by the receiver, the UART will interpret this as a framing error.
7.2.4.6 Voting Logic
The vote logic block provides jitter tolerance and noise immunity by sampling with respect to the peripheral
clock and using voting techniques to clean up the samples. The voting is implemented by sampling the
incoming signal constantly on the rising edge of clock. The receiver is provided with the majority vote
value, which is two out of the three samples.
The vote logic captures a sample on every rising edge of the clock, but the receiver takes its value in the
middle of the sample frame using 16x oversampling. The idle character may be longer or shorter than 16
counts, but the receiver looks for a 1 to 0 transition. Then it starts to count the start bit but does not capture
it in the FIFO. The start bit is validated upon receiving zeros for seven consecutive bit times following the
1 to 0 transition. Once the counter reaches F hex, it starts counting the next bit and captures it in the middle
of the sampling frame. All data bits are captured in the same manner. Once the stop bit is detected, the
receiver shift register data is parallel shifted to the receiver FIFO.
7.2.5 UART Registers
The following paragraphs provide detailed descriptions of UART registers.
7.2.5.1 UART Control Register (UCON)
UCON is used to specify transmission parameters, such as flow control, stop bits, parity, and so on.
TST—Test Loop-Back:
This bit sets whether the MC72000 is placed into test loop-back mode where the TXD and RXD signals
are connected.
Table 27. Majority Vote Results
Samples
Vote
000
101
001
111
0
1
0
1
UCONBase + $000
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
R
W
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
7
6
5
4
3
2
1
0
R
W
TST
MRX
R
1
= writes have no effect and terminate without transfer error exception
MTXR FCE
FCP
XTIM
SEL
TX_OEN_
B
1
CONT
X
0
SB
ST2
EP
PEN
RXE
TXE
RST
0
1
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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| MC7220C-100M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20 CORE 100M |
| MC7220C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-20C 20CORE 25M 制造商:pro-power 功能描述:CABLE, DEF 7-2-20C, 20CORE, 25M |
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| MC7225C-25M RI-BLK | 制造商:Farnell / Pro-Power 功能描述:CABLE DEF 7-2-25C 25CORE 25M 制造商:pro-power 功能描述:MULTICORE, 25, 7/0.2MM, 25M, BLACK 制造商:pro-power 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M 制造商:PRIVATE LABEL 功能描述:CABLE, DEF 7-2-25C, 25CORE, 25M, Reel Length (Imperial):82ft, Reel Length (Metri |
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