參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 120/156頁
文件大?。?/td> 1782K
代理商： MC72000
120
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
Bit clock—Used to serially clock the data bits in and out of the SSI port.
Word clock—Used to count the number of data bits per word (8, 10, 12, or 16 bits).
Frame clock—Used to count the number of words in a frame.
The bit clock is used to serially clock the data. It is visible on the serial transmit clock (STCK) and serial
receive clock (SRCK) pins. The word clock is an internal clock used to determine when transmission of an
8-, 10-, 12-, or 16-bit word has completed. The word clock in turn then clocks the frame clock, which marks
the beginning of each frame. The frame clock can be viewed on the STFS and SRFS pins. The bit clock can
be received from an SSI clock pin or can be generated from the peripheral clock passed through a divider,
as shown in Figure 81.
Figure 79. SSI Clocking (8-bit words, 3 time-slots/frame)
Figure 80. SSI Clock Generation
7.4.8.1 Description of Clock Operation
The following section describes clock operation.
7.4.8.1.1
SSI Clock and Frame Sync Generation
Data clock and frame sync signals can be generated internally by the SSI or can be obtained from external
sources. If internally generated, the SSI clock generator is used to derive bit clock and frame sync signals
Table 61. Clock Summary
Clock
Priority
Source
Characteristics
STCK
Internal/External
Transmit data is changed on the rising edge of this clock. The TSCKP
bit of the SCR2 register can invert the clock if needed.
Receive data is captured on the falling edge of this clock. The RSCKP
bit of the SCSR register can invert the clock if needed.
Transmit frames begin with the rising edge of this signal. See the
definition of the TEFS bit of the SCR2 register for timing options. The
TFSI bit can invert this signal if needed.
Receive frames begin with the rising edge of this signal. See the
definition of the REFS bit of the SCSR register for timing options.
SRCK
Internal/External
STFS
Internal/External
SRFS
Internal/External
TS0
TS1
TS2
TS0
TS1
TS2
Frame n
Frame n+1
STCK, SRCK
WORD_CLOCK
STFS, SRFS
data
Serial Bit Clock
(STCK, SRCK)
Word Divider
(/8, /10, /12, /16)
Word clock
Frame Divider
(/1 to /32)
Frame clock
STFS, SRFS
F
For More Information On This Product,
n
.
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