參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無線
文件頁數(shù)： 72/156頁
文件大小： 1782K
代理商： MC72000
72
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.3.7.5 CSPI Test Register (TESTREG)
Figure 40. CSPI Test Register (TESTREG)
TESTREG is a 32-bit register that controls how the serial peripheral interface operates and reports status.
The high 16 bits are reserved bits and are always read as 0.
TEST—Test
1 = Sample period counter increment value set to 0x0421
0 = Sample period counter increment value set to 0x1
LOOP—Internal Loop Back
1 = Internal loop back enabled
0 = Internal loop back disabled
INIT—Initialize State Machine and Edge Detect
This bit is used for test purposes only.
SYN—Synchronous Transfer
This bit is used for test purposes only.
SSTATUS[3:0]—State Machine Status
This bit field indicates the state machine status. These bits are used for test purposes only.
Table 33. SSTATUS[3:0] Encoding
Register address: Base + 0x10
31
30
29
28
27
26
25
24
Reserved
0
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
TEST LOOP
INIT
SYN
SSTATUS[3:0]
RXCNT[3:0]
TXCNT[3:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
SSTATUS[3:0]
Function
Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
IDLE
EXCH
SSB0
T2
BUSY
ACTIVE
WAITCNT
CK2SSB1
T3
SSB1
WAITCNT2
READY
waiting for EXCH or SLAVE_ENABLE
Waiting for DATAREADY_B
Set SS_B active
SS_B output low to first SPI_CK edge
Delay SPI_CK edge
Start data
Count data bits
Last SCLK edge to SS_B output high delay
Insert SS_B high value
Slave Select is disabled
SS_B output pulse width
Wait for DATAREADY_B active
F
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