參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 74/156頁
文件大?。?/td> 1782K
代理商： MC72000
74
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
* IPbus clock period). If this constraint is violated, new transmissions will be synchronized to the 32 kHz
clock but each 32 kHz clock will not produce a new transmitted data word.
CSRC—Clock source for period counter
1 = 32.68 kHz
0 = Bit clock
WAIT—Number of Clocks Inserted between Data Transactions
Table 36 shows WAIT bit field encoding.
7.3.7.7 CSPI Soft Reset Register (RESETREG)
Figure 42. CSPI Soft Reset Register (RESETREG)
RESETREG is a 32-bit register. Writing a 1 to the START bit resets the CSPI module. All registers in the
CSPI are reset including the CONTROLREG.
START — Soft Reset
The soft reset is extended by two clock cycles so there must be at least three IP_BUS clocks before any
attempt is made to write the CONTROLREG to initiate CSPI operation after the START bit is written.
1 = Soft reset
0 = No soft reset
7.3.8 Functional Description
7.3.8.1 General
The CSPI module allows full-duplex, synchronous, serial communication between the MC72000 and
peripheral devices. Software can poll the CSPI status flags or CSPI operation can be interrupt-driven.
Figure 43 shows the generic CSPI timing.
Table 36. WAIT Encoding
WAIT
Function
0x0000
0x0001
0x0002
.
.
.
0x7FFF
0 Clock
1 Clock
2 Clocks
.
.
.
32768 Clocks
Register address: Base + 0x1C
31
30
29
28
27
26
25
24
Reserved
0
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
W
STAR
T
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
F
For More Information On This Product,
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