參數(shù)資料
型號： MC72000
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍牙無線
文件頁數(shù)： 107/156頁
文件大小： 1782K
代理商： MC72000
MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
107
7.4.6.1.1.2
Normal Mode Receive
The conditions for data reception from the SSI are as follows:
1. Set the SCSR, SRXCR, SCR2, and SOR registers to select normal mode operation, define
the receive clock, receive frame sync and frame structure required for proper system
operation.
2. Enable SSI (SSIEN = 1).
3. Enable RXFIFO (RFEN=1) and configure receive watermark (RFWM=n) if RXFIFO is
used.
4. Enable receive interrupts.
5. Set the RE bit (RE = 1) to enable the receiver operation on the next frame sync boundary.
Figure 72 and Table 53 describes the functions performed during receive operation in this mode.
5
If the TIE bit is set, enabling transmit interrupts,
then:
(Other options for processing the data transfer
are either polling or DMA transfers.)
The TXSR is shifted on the next rising edge of
STCK and the next bit appears on the STXD
pin
When WL bits (see Section 7.4.5.2.7, “SSI
Transmit and Receive Control Registers
(STXCR, SRXCR)”) have been sent, the STXD
is tri-stated
Transmit under-run (setting the TUE bit of the
SCSR register) is prevented by
2
:
Transmit interrupt occurs
when TDE set
Transmit interrupt occurs when TFE set
6
7
8
New data is written to the
STX before the TXSR tries
to obtain new transmit data
at the next frame sync
New data is written to the STX before the
TXSR tries to obtain data from an empty
TXFIFO (this can be several frame times)
9 Repeat at step 1 on the next frame sync
3
1.The STXD output signal is disabled except during the data transmission period.
2.See the description of the TUE bit in Section 7.4.5.2.8, “SSI Control/Status Register (SCSR),” for a description of what
happens when the TUE bit is set.
3.The frame sync must not occur earlier than what is configured in the STXCR as documented in Section 7.4.5.2.7, “SSI
Transmit and Receive Control Registers (STXCR, SRXCR).”
Table 52. Normal Mode Transmit Operations
Step
TXFIFO Disabled
(See Figure 71)
TXFIFO Enabled
(No Figure Available)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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