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參數(shù)資料
| 型號： | MC72000 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Integrated Bluetooth Radio |
| 中文描述： | 集成藍(lán)牙無線 |
| 文件頁數(shù)： | 91/156頁 |
| 文件大小： | 1782K |
| 代理商： | MC72000 |
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
91
REFS—Receive Early Frame Sync
This bit controls when the frame sync is initiated for the receive section. See Figure 60 for an example
timing diagram of the FS options.
1 = The frame sync is initiated one bit before the data is received
The frame sync is disabled after one bit-for-bit length frame sync and after one word-for-word
length frame sync.
0 = When the REFS bit is cleared, the frame sync is initiated as the first bit of data is received
RDR—Receive Data Ready Flag
This flag bit is set when receive data register (SRX) or receive FIFO (RXFIFO) is loaded with a new
value.
RDR is cleared when the CPU reads the SRX register. If RXFIFO is enabled, RDR is cleared when
receive FIFO is empty.
If the RIE bit is set, a receive data interrupt request is issued when the RDR bit is set. The interrupt
request vector depends on the state of the receiver overrun (ROE) bit (in the SCSR). The RDR bit is
cleared by POR and SSI reset.
TDE—Transmit Data Register Empty
This flag bit is set when there is no data waiting to be transferred to the TXSR register. If the transmit
FIFO (TXFIFO) is enabled, this occurs when there is at least one empty slot in STX or TXFIFO. If the
TXFIFO is not enabled, this occurs when the STX is empty, that is, when the contents of the STX
register are transferred into the transmit shift register (TXSR). When set, the TDE bit indicates that data
should be written to the STX register or to the STSR before the transmit shift register becomes empty,
or an underrun error will occur.
The TDE bit is cleared when data is written to the STX register or to the STSR to disable transmission
of the next time slot. If the TIE bit is set, an SSI transmit data interrupt request is issued when the TDE
bit is set. The vector of the interrupt depends on the state of the TUE bit (in the SCSR). The TDE bit is
set by power-on and SSI reset.
ROE—Receive Overrun Error
This flag bit is set when the receive shift register (RXSR) is filled and ready to transfer to the SRX
register or the RXFIFO register (when enabled), and these registers are already full. If the receive FIFO
is enabled, this is indicated by the receive FIFO full (RFF) bit else this is indicated by the receive data
ready (RDR) bit being set. The RXSR is not transferred in this case.
NOTE:
When using the RXFIFO with a watermark other than 8, the ROE bit does
not mean that data has been lost. The RXCNT field of the SFCSR should
be checked to determine the likelihood of actual data loss.
A receive overrun error does not cause any interrupts. However, when the ROE bit is set, it causes a
change in the interrupt vector used, allowing the use of a different interrupt handler for a receive overrun
condition. If a receive interrupt occurs with the ROE bit set, the receive data with exception status
interrupt is generated. If a receive interrupt occurs with the ROE bit cleared, the receive data interrupt
is generated. The ROE bit is cleared by power-on or SSI reset and is cleared by reading the SCSR with
the ROE bit set, followed by reading the SRX register. Clearing the RE bit does not affect the ROE bit.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
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