參數(shù)資料
型號(hào)： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無(wú)線
文件頁(yè)數(shù)： 88/156頁(yè)
文件大?。?/td> 1782K
代理商： MC72000
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88
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
0 = When the PSR bit is cleared, the fixed prescaler is bypassed.
WL[1:0]—Word Length Control
This bit field is used to select the length of the data words being transferred by the SSI. Word lengths
of 8, 10, 12, or 16 bits can be selected. Table 40 shows WL[1:0] bit field encoding.
Table 40. WL[1:0] Encoding
These bits control the word length divider shown in the SSI clock generator. The WL control bits also
control the frame sync pulse length when the TFSL bit is cleared.
DC[4:0]—Frame Rate Divider Control
This bit field controls the divide ratio for the programmable frame rate dividers. The divide ratio
operates on the word clock.
In normal mode, this ratio determines the word transfer rate. The divide ratio ranges from 1 to 32
(DC[4:0] = 00000 to 11111) in normal mode. A divide ratio of one (DC=00000) provides continuous
periodic data word transfer. A bit-length sync must be used in this case.
In network mode, this ratio sets the number of words per frame. The divide ratio ranges from 2 to 32
(DC[4:0] = 00001 to 11111) in network mode. A divide ratio of one (DC=00000) in network mode is a
special case (on demand mode) that is not supported in this implementation.
PM[7:0]—Prescale Modulus Select
This bit field specifies the divide ratio of the prescale divider in the SSI clock generator. This prescaler
is used only in internal clock mode to divide the internal clock of the core. A divide ratio from 1 to 256
(PM[7:0] = $00 to $FF) can be selected. The bit clock output is available at the STCK or SRCK clock
pins. The bit clock on the SSI can be calculated from the peripheral clock value using the following
equation:
f
FIX_CLK
=
f
IP_bus_CLK
/4if DIV4DIS = 0
f
FIX_CLK
=
f
IP_bus_CLK
if DIV4DIS = 1
f
INT_BIT_CLK
= f
FIX_CLK
/[4 x (7 x PSR + 1) x (PM + 1)]
where PM = PM[7:0]
f
FRAME_SYN_CLK
= (f
INT_BIT_CLK
)/[(DC + 1) x WL]
where DC = DC[4:0] and WL = 8, 10, 12, or 16
For example, with 8-bit words operating in normal mode, if an 8 kHz sampling rate is desired the
following parameters can be used:
f
IP_bus_CLK
= f
SYSTEM_CLK
/ 2 = 120 MHz / = 60 mhz
f
FIX_CLK
=
f
IP_bus_CLK
= 60 MHzDIV4DIS = 1
f
INT_BIT_CLK
= f
FIX_CLK
/[4 x (7 x PSR + 1) x (PM + 1)]
= 60 MHz / [4 x 1 x 117] = 128.2 kHzPS = 0, PM = 116
f
FRAME_SYN_CLK
= (f
INT_BIT_CLK
)/[(DC + 1) x WL]DC = 1
= 128 kHz / [2 x 8] = 8.012 kHz
WL[1:0]
Number of Bits/Word
00
01
10
11
8
10
12
16
F
For More Information On This Product,
n
.
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