參數(shù)資料
型號: MC72000
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Integrated Bluetooth Radio
中文描述: 集成藍牙無線
文件頁數(shù): 78/156頁
文件大?。?/td> 1782K
代理商: MC72000
78
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Hardware Functional Description
7.4 Synchronous Serial Interface (SSI)
7.4.1 Overview
This section describes the Synchronous Serial Interface (SSI), and discusses the architecture, the
programming model, the operating modes, and initialization of the SSI. The SSI is a full-duplex, serial port
that allows the MC72000 to communicate with a variety of serial devices, including industry-standard
CODECs, other MCUs, and peripheral devices that implement the Motorola Serial Peripheral Interface
(SPI). It is typically used to transfer samples in a periodic manner. The SSI consists of independent
transmitter and receiver sections with independent clock generation and frame synchronization.
The first-time reader should read Section 7.4.2, “Features,” and then Section 7.4.6, “Functional
Description.”
7.4.2 Features
SSI features include the following:
Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or
shared internal/external clocks and frame syncs
Normal mode operation using frame sync
Network mode operation allowing multiple devices to share the port with as many as thirty-two time
slots
Gated clock mode operation requiring no frame sync
Programmable internal clock divider
Programmable word length (8, 10, 12, or 16 bits)
Program options for frame sync and clock generation
SSI power-down feature
7.4.3 Block Diagram
NOTE:
The MC72000 only supports synchronous mode, which limits the number
of pins available.
Figure 49 shows a block diagram of the SSI. It consists of three control registers to set up the port, one
status/control register, separate transmit and receive circuits with FIFO registers, and separate serial clock
and frame sync generation for the transmit and receive sections.
Pause between data word
0
ns
1.T = CSPI clock period
2.T = CSPI clock period
3.T = CSPI clock period
4.WAIT = Number of sysclk or 32.768 kHz clocks per sample period control register.
Table 37. CSPI Timing
Num
Characteristic
3.3V
Unit
Minimum
Maximum
F
For More Information On This Product,
n
.
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