參數(shù)資料
型號(hào)： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無(wú)線
文件頁(yè)數(shù)： 148/156頁(yè)
文件大?。?/td> 1782K
代理商： MC72000
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148
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
MOTOROLA
Applications Information
BTASP key features:
Overall system pass-band is 280 Hz to 3.45 kHz (-3 dB), measured with white noise.
Out-of-band attenuation above 4 kHz is at least 80 dB, measured with white noise.
SNR at 1.020 kHz with maximal signal level (max. volume setting) is above 60 dB, measured with
a 1.020 kHz fixed sine.
The latency measured with a short sine pulse (one-way latency) is as follows:
— Using HV1 packets: 4.9 ms
— Using HV2 packets: 6.1 ms
— Using HV3 packets: 7.4 ms
Phase jitter: < 5° C measured for a 1.020 kHz sine.
10.10 Timing and Low Power Mode
The timing for the Power on reset (POR) and the implementation of the low power modes is thoroughly
described in
MC71000/MC72000 Wake-Up, Reset, and Host Clock Request Sequences Application Note
(document number AN2340/D).
10.11 UART Interface
The host interface is a standard HCI UART (H:4) transport layer, where all communication from
application, upper stack and file system passes through.
The UART transport layer supports baud rate ranging from 1200 to 1843200 bit/s.
The MC72000 UART interface can be configured to be a 4-, 5-, or 6-wire interface.
The default baud rate upon start up can be configured. See
Motorola Bluetooth File System, Overview
Application Note
(document number 94001481001),
UART/SSI Configuration User′s Guide
(document
number 94001481900) and
Motorola Bluetooth File System, Host-based General Application Note
(document number 94001481003) for more details.
10.12 JTAG Interface
The JTIC interface intended for debug and production test purposes, may be wired to an external JTAG
controller. In this case, refer to the external document
Production Test Application Note
(document
number 94001481100) in Section 5.2, “Document References,” and other implementation guidance
documents in this section.
If JTAG is omitted from design, all JTAG interface pins must be left open. TRST_B may be pulled-down
and TMS may be pulled-up to enhance reliability, and to ensure that the JTAG interface stays disabled at
all times. All JTAG input pins has internal pull-up/downs and cannot be disabled as normal GPIO pins can.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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