參數(shù)資料
型號(hào)： MC72000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Integrated Bluetooth Radio
中文描述： 集成藍(lán)牙無(wú)線
文件頁(yè)數(shù)： 59/156頁(yè)
文件大?。?/td> 1782K
代理商： MC72000
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MOTOROLA
MC72000
Advance Information Data Sheet
Go to: www.freescale.com
59
FE—Frame/Stop Bit Error
This read-only bit indicates, while HIGH, that the current character had a framing error (missing stop
bit or break condition). The data is possibly corrupted. This bit is updated for each character read from
the FIFO. The FE bit is cleared by UART reset or by reading the USTAT register.
1 = Framing error occurred
0 = No framing error
PE—Parity Error
This read-only bit indicates, while HIGH, that the current character was detected with a parity error. The
data is possibly corrupted. This bit is updated for each character read from the FIFO. While parity is
disabled, this bit always reads zero. The PE bit is cleared by UART reset or by reading the USTAT
register.
1 = Parity error occurred
0 = No parity error
SE—Start Bit Error
This read-only bit indicates, while HIGH, that the current character had a framing error (missing start
bit.) The data is possibly corrupted. This can occur when a start bit (RXD = 0) is found, but is not
verified at the center of the bit (for example, glitch). This bit is updated for each character read from the
FIFO. The SE bit is cleared by UART reset or by reading the USTAT register.
1 = Start bit error occurred
0 = No start bit error
7.2.5.3 UART Data Register (UDATA)
UDATA fills the UART transmit FIFO buffer with bytes that are to be transmitted, and to read the received
bytes from the UART receive FIFO buffer.
It is possible to read/write 1 byte per access.
RXDATA[7:0]—Received Byte
This bit field contains the 8-bit data that has been received.
TXDATA[7:0]—Byte To Transmit
This bit field contains the 8-bit data to be transmitted.
7.2.5.4 UART Buffer Control Registers
The UART buffers use threshold values to generate interrupts. These thresholds can be used to specify that
an interrupt should be generated before the transmit FIFO has become completely empty, or some time
UDATABase + $008
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
R
W
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
RXDATA
TXDATA
Undefined
3
2
1
0
R
W
RST
0
0
0
0
0
0
0
0
= writes have no effect and terminate without transfer error exception
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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