參數(shù)資料
型號: LXP710PE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 77/84頁
文件大小: 1108K
代理商: LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
LXP710
Datasheet
77
Figure 17. Microprocessor Write Cycle
Intel Mode
Table 125. Microprocessor Read Cycle Specifications
Intel Mode
(
Figure 18
)
Parameter
Sym
Min
Typ
1
Max
Unit
Test Conditions
D<0:7> valid after
CS
,
RD
assertion
t
DATA
45
60
ns
D<0:7> keep valid after
CS
,
RD
negation
t
DATN
20
ns
Allowed width of
CS
t
CPW
80
ns
Allowed width of
RD
t
RPW
80
ns
Address setup time to
CS
,
RD
assertion
t
ASU
50
ns
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
t
ASU
t
WPW
Address (A<0:6>)
D<0:7>
CS
t
DSU
t
CPW
t
DHT
t
WSU
(R/W) WR
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