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參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 16/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
16
Datasheet
Several bits can be set for error injection testing on a per loop basis. The outgoing febe and bpv bits
can be injected as single bit errors. The CRC can be set for continuous error generation. Registers
L
n
OHCTL, listed in
Table 6
through
Table 8
, control this activity.
The transmitted Z-bits and eoc bits are set by the microprocessor interface. The Z-bit transmit
registers are MXL1Z
x
in
Table 39
through
Table 62
, MXL2Z
x
in
Table 63
through
Table 86
,
MXL3Z
x
in
Table 87
through
Table 110
. The eoc transmit registers are MXL1EOC in
Table 45
and
Table 46
, MXL2EOC in
Table 69
and
Table 70
, MXL3EOC in
Table 93
and
Table 94
. In general
applications, the eoc is used by the HTU-C to transmit a command continuously to the HTU-R unit
until the HTU-R echoes the same command back to the HTU-C three times. ETR 152 recommends
some common commands that might be used, but it is up to each vendor to specify detailed
implementation. The only defined Z-bits are the first three used for loop identification. Other Z-bits
are reserved for vendor use.
The PAT_GEN block generates a QRSS pattern and can be set to generate an error in that pattern.
The QRSS is put in place of the E1 data for testing purposes. The QRSS signal is on a per loop
basis and is controlled by the PATCTL register as described in
Table 22 on page 34
.
Figure 3. MX Process
FIFO
MX_E1_CTL
E1 Data
AIS
E1_NMCK
E1 CLKI
E1FRMI
FRCMXAIS
PAT_GEN
CRC6
LPx_DATA
HDSL_MX
LOSD, BPV, febe
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